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[MLIR] Mark LLVM::FMAOp as legal #144671

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Merged
merged 3 commits into from
Jun 18, 2025
Merged

[MLIR] Mark LLVM::FMAOp as legal #144671

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[MLIR] Mark LLVM::FMAOp as legal since we can lower to NVVM
chelini Jun 18, 2025
341820e
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chelini Jun 18, 2025
870f194
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chelini Jun 18, 2025
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8 changes: 4 additions & 4 deletions mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -429,10 +429,10 @@ void mlir::configureGpuToNVVMConversionLegality(ConversionTarget &target) {
target.addLegalDialect<::mlir::NVVM::NVVMDialect>();
target.addIllegalDialect<gpu::GPUDialect>();
target.addIllegalOp<LLVM::CopySignOp, LLVM::CosOp, LLVM::ExpOp, LLVM::Exp2Op,
LLVM::FAbsOp, LLVM::FCeilOp, LLVM::FFloorOp, LLVM::FMAOp,
LLVM::FRemOp, LLVM::LogOp, LLVM::Log10Op, LLVM::Log2Op,
LLVM::PowOp, LLVM::RoundEvenOp, LLVM::RoundOp,
LLVM::SinOp, LLVM::SqrtOp>();
LLVM::FAbsOp, LLVM::FCeilOp, LLVM::FFloorOp, LLVM::FRemOp,
LLVM::LogOp, LLVM::Log10Op, LLVM::Log2Op, LLVM::PowOp,
LLVM::RoundEvenOp, LLVM::RoundOp, LLVM::SinOp,
LLVM::SqrtOp>();

// TODO: Remove once we support replacing non-root ops.
target.addLegalOp<gpu::YieldOp, gpu::GPUModuleOp>();
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2 changes: 1 addition & 1 deletion mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
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Expand Up @@ -1027,7 +1027,7 @@ module attributes {transform.with_named_sequence} {
legal_ops = ["func.func", "gpu.module", "gpu.yield"],
illegal_dialects = ["gpu"],
illegal_ops = ["llvm.copysign", "llvm.cos", "llvm.exp", "llvm.exp2", "llvm.fabs", "llvm.fceil",
"llvm.ffloor", "llvm.fma", "llvm.frem", "llvm.log", "llvm.log10", "llvm.log2", "llvm.pow",
"llvm.ffloor", "llvm.frem", "llvm.log", "llvm.log10", "llvm.log2", "llvm.pow",
"llvm.roundeven", "llvm.round", "llvm.sin", "llvm.sqrt"],
partial_conversion
} : !transform.any_op
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14 changes: 13 additions & 1 deletion mlir/test/Integration/GPU/CUDA/dump-ptx.mlir
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Expand Up @@ -2,7 +2,7 @@
// RUN: | mlir-opt -gpu-lower-to-nvvm-pipeline -debug-only=serialize-to-isa \
// RUN: 2>&1 | FileCheck %s

// CHECK: Generated by LLVM NVPTX Back-End
// CHECK-LABEL: Generated by LLVM NVPTX Back-End
// CHECK: .visible .func kernel_a()
// CHECK: ret;
gpu.module @bar {
Expand All @@ -11,3 +11,15 @@ gpu.module @bar {
llvm.return
}
}

// CHECK-LABEL: Generated by LLVM NVPTX Back-End
// CHECK: .visible .func ({{.+}}) fma(
// CHECK: fma.rn.f32

gpu.module @foo {
llvm.func @fma(%arg0: f32, %arg1: f32) -> f32
attributes { gpu.kernel } {
%res = llvm.intr.fma (%arg0, %arg1, %arg1) : (f32, f32, f32) -> f32
llvm.return %res : f32
}
}
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