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[LLVM][DecoderEmitter] Add option to use function table in decodeToMCInst #144814
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,84 @@ | ||
| // RUN: llvm-tblgen -gen-disassembler -use-fn-table-in-decode-to-mcinst -I %p/../../include %s | FileCheck %s | ||
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| include "llvm/Target/Target.td" | ||
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| def archInstrInfo : InstrInfo { } | ||
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| def arch : Target { | ||
| let InstructionSet = archInstrInfo; | ||
| } | ||
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| let Namespace = "arch" in { | ||
| def R0 : Register<"r0">; | ||
| def R1 : Register<"r1">; | ||
| def R2 : Register<"r2">; | ||
| def R3 : Register<"r3">; | ||
| } | ||
| def Regs : RegisterClass<"Regs", [i32], 32, (add R0, R1, R2, R3)>; | ||
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| class TestInstruction : Instruction { | ||
| let Size = 1; | ||
| let OutOperandList = (outs); | ||
| field bits<8> Inst; | ||
| field bits<8> SoftFail = 0; | ||
| } | ||
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| // Define instructions to generate 4 cases in decodeToMCInst. | ||
| // Lower 2 bits define the number of operands. Each register operand | ||
| // needs 2 bits to encode. | ||
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| // An instruction with no inputs. Encoded with lower 2 bits = 0 and upper | ||
| // 6 bits = 0 as well. | ||
| def Inst0 : TestInstruction { | ||
| let Inst = 0x0; | ||
| let InOperandList = (ins); | ||
| let AsmString = "Inst0"; | ||
| } | ||
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| // An instruction with a single input. Encoded with lower 2 bits = 1 and the | ||
| // single input in bits 2-3. | ||
| def Inst1 : TestInstruction { | ||
| bits<2> r0; | ||
| let Inst{1-0} = 1; | ||
| let Inst{3-2} = r0; | ||
| let InOperandList = (ins Regs:$r0); | ||
| let AsmString = "Inst1"; | ||
| } | ||
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| // An instruction with two inputs. Encoded with lower 2 bits = 2 and the | ||
| // inputs in bits 2-3 and 4-5. | ||
| def Inst2 : TestInstruction { | ||
| bits<2> r0; | ||
| bits<2> r1; | ||
| let Inst{1-0} = 2; | ||
| let Inst{3-2} = r0; | ||
| let Inst{5-4} = r1; | ||
| let InOperandList = (ins Regs:$r0, Regs:$r1); | ||
| let AsmString = "Inst2"; | ||
| } | ||
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| // An instruction with three inputs. Encoded with lower 2 bits = 3 and the | ||
| // inputs in bits 2-3 and 4-5 and 6-7. | ||
| def Inst3 : TestInstruction { | ||
| bits<2> r0; | ||
| bits<2> r1; | ||
| bits<2> r2; | ||
| let Inst{1-0} = 3; | ||
| let Inst{3-2} = r0; | ||
| let Inst{5-4} = r1; | ||
| let Inst{7-6} = r2; | ||
| let InOperandList = (ins Regs:$r0, Regs:$r1, Regs:$r2); | ||
| let AsmString = "Inst3"; | ||
| } | ||
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| // CHECK-LABEL: decodeFn0 | ||
| // CHECK-LABEL: decodeFn1 | ||
| // CHECK-LABEL: decodeFn2 | ||
| // CHECK-LABEL: decodeFn3 | ||
| // CHECK-LABEL: decodeToMCInst | ||
| // CHECK: static constexpr DecodeFnTy decodeFnTable[] | ||
| // CHECK-NEXT: decodeFn0, | ||
| // CHECK-NEXT: decodeFn1, | ||
| // CHECK-NEXT: decodeFn2, | ||
| // CHECK-NEXT: decodeFn3, | ||
| // CHECK: return decodeFnTable[Idx] | ||
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