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[MLIR][AArch64] Simplify LowerContractionToSVEI8MMPattern.cpp:getExtOperand (NFC) #144909

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Merged
momchil-velikov merged 1 commit into from
Jun 23, 2025
Merged

[MLIR][AArch64] Simplify LowerContractionToSVEI8MMPattern.cpp:getExtOperand (NFC) #144909

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20 changes: 8 additions & 12 deletions mlir/lib/Dialect/ArmSVE/Transforms/LowerContractionToSVEI8MMPattern.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ namespace {
//
// Return success only for extensions from `i8` to `i32`.
template <typename Op>
std::optional<Value> getExtOperand(Value v, Type i8Ty, Type i32Ty) {
std::optional<Value> getExtOperand(Value v) {

static_assert(llvm::is_one_of<Op, arith::ExtSIOp, arith::ExtUIOp>::value,
"Must be instantiated with either sign- or zero- extension op");
Expand All @@ -50,7 +50,7 @@ std::optional<Value> getExtOperand(Value v, Type i8Ty, Type i32Ty) {
if (!extOp) {
if constexpr (std::is_same<Op, arith::ExtSIOp>::value) {
auto vTy = cast<VectorType>(v.getType());
if (vTy.getElementType() != i8Ty)
if (!vTy.getElementType().isSignlessInteger(8))
return {};
return v;
}
Expand All @@ -61,11 +61,11 @@ std::optional<Value> getExtOperand(Value v, Type i8Ty, Type i32Ty) {
// operation type, check it's extended from `i8` to `i32`.
auto inOp = extOp.getIn();
auto inTy = dyn_cast<VectorType>(inOp.getType());
if (!inTy || inTy.getElementType() != i8Ty)
if (!inTy || !inTy.getElementType().isSignlessInteger(8))
return {};

auto outTy = dyn_cast<VectorType>(extOp.getType());
if (!outTy || outTy.getElementType() != i32Ty)
if (!outTy || !outTy.getElementType().isSignlessInteger(32))
return {};

return inOp;
Expand Down Expand Up @@ -199,27 +199,23 @@ class LowerContractionToSVEI8MMPattern
// operands are supported, but they are lowered to different operations.
// Determine which is the appropriate operation to lower to.
MMLA mmlaOp = MMLA::Signed;
auto maybeLhs = getExtOperand<arith::ExtSIOp>(
op.getLhs(), rewriter.getI8Type(), rewriter.getI32Type());
auto maybeLhs = getExtOperand<arith::ExtSIOp>(op.getLhs());
if (!maybeLhs) {
mmlaOp = MMLA::Unsigned;
maybeLhs = getExtOperand<arith::ExtUIOp>(
op.getLhs(), rewriter.getI8Type(), rewriter.getI32Type());
maybeLhs = getExtOperand<arith::ExtUIOp>(op.getLhs());
}
if (!maybeLhs)
return rewriter.notifyMatchFailure(
op, "LHS is not a sign- or zero- extended i8");

auto maybeRhs = getExtOperand<arith::ExtSIOp>(
op.getRhs(), rewriter.getI8Type(), rewriter.getI32Type());
auto maybeRhs = getExtOperand<arith::ExtSIOp>(op.getRhs());
if (maybeRhs) {
if (mmlaOp == MMLA::Unsigned)
mmlaOp = MMLA::Mixed;
} else {
if (mmlaOp == MMLA::Signed)
mmlaOp = MMLA::MixedSwapped;
maybeRhs = getExtOperand<arith::ExtUIOp>(
op.getRhs(), rewriter.getI8Type(), rewriter.getI32Type());
maybeRhs = getExtOperand<arith::ExtUIOp>(op.getRhs());
}
if (!maybeRhs)
return rewriter.notifyMatchFailure(
Expand Down
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