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[AArch64] Enable dead register definitions at O0 #145174

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[AArch64] Enable dead register definitions at O0 #145174

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80e63f4
Pre-commit test
AZero13 Jun 21, 2025
edff84a
Enable dead register definitions at O0
AZero13 Jun 21, 2025
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5 changes: 3 additions & 2 deletions llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -803,8 +803,9 @@ bool AArch64PassConfig::addILPOpts() {

void AArch64PassConfig::addPreRegAlloc() {
// Change dead register definitions to refer to the zero register.
if (TM->getOptLevel() != CodeGenOptLevel::None &&
EnableDeadRegisterElimination)
// This is beneficial even at -O0 as we can show CMP/CMN in the assembler
// output.
if (EnableDeadRegisterElimination)
addPass(createAArch64DeadRegisterDefinitions());

// Use AdvSIMD scalar instructions whenever profitable.
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-outline_atomics.ll
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Expand Up @@ -121,7 +121,7 @@ define dso_local void @store_atomic_i128_aligned_unordered(i128 %value, ptr %ptr
; -O0: eor x8, x0, x8
; -O0: eor x9, x1, x9
; -O0: orr x8, x8, x9
; -O0: subs x8, x8, #0
; -O0: cmp x8, #0
;
; -O1-LABEL: store_atomic_i128_aligned_unordered:
; -O1: ldxp xzr, x8, [x2]
Expand All @@ -136,7 +136,7 @@ define dso_local void @store_atomic_i128_aligned_monotonic(i128 %value, ptr %ptr
; -O0: eor x8, x0, x8
; -O0: eor x9, x1, x9
; -O0: orr x8, x8, x9
; -O0: subs x8, x8, #0
; -O0: cmp x8, #0
;
; -O1-LABEL: store_atomic_i128_aligned_monotonic:
; -O1: ldxp xzr, x8, [x2]
Expand All @@ -151,7 +151,7 @@ define dso_local void @store_atomic_i128_aligned_release(i128 %value, ptr %ptr)
; -O0: eor x8, x0, x8
; -O0: eor x9, x1, x9
; -O0: orr x8, x8, x9
; -O0: subs x8, x8, #0
; -O0: cmp x8, #0
;
; -O1-LABEL: store_atomic_i128_aligned_release:
; -O1: ldxp xzr, x8, [x2]
Expand All @@ -166,7 +166,7 @@ define dso_local void @store_atomic_i128_aligned_seq_cst(i128 %value, ptr %ptr)
; -O0: eor x8, x0, x8
; -O0: eor x9, x1, x9
; -O0: orr x8, x8, x9
; -O0: subs x8, x8, #0
; -O0: cmp x8, #0
;
; -O1-LABEL: store_atomic_i128_aligned_seq_cst:
; -O1: ldaxp xzr, x8, [x2]
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-rcpc.ll
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Expand Up @@ -125,7 +125,7 @@ define dso_local void @store_atomic_i128_aligned_unordered(i128 %value, ptr %ptr
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
; -O0: orr x8, x8, x11
; -O0: subs x8, x8, #0
; -O0: cmp x8, #0
;
; -O1-LABEL: store_atomic_i128_aligned_unordered:
; -O1: ldxp xzr, x8, [x2]
Expand All @@ -144,7 +144,7 @@ define dso_local void @store_atomic_i128_aligned_monotonic(i128 %value, ptr %ptr
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
; -O0: orr x8, x8, x11
; -O0: subs x8, x8, #0
; -O0: cmp x8, #0
;
; -O1-LABEL: store_atomic_i128_aligned_monotonic:
; -O1: ldxp xzr, x8, [x2]
Expand All @@ -163,7 +163,7 @@ define dso_local void @store_atomic_i128_aligned_release(i128 %value, ptr %ptr)
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
; -O0: orr x8, x8, x11
; -O0: subs x8, x8, #0
; -O0: cmp x8, #0
;
; -O1-LABEL: store_atomic_i128_aligned_release:
; -O1: ldxp xzr, x8, [x2]
Expand All @@ -182,7 +182,7 @@ define dso_local void @store_atomic_i128_aligned_seq_cst(i128 %value, ptr %ptr)
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
; -O0: orr x8, x8, x11
; -O0: subs x8, x8, #0
; -O0: cmp x8, #0
;
; -O1-LABEL: store_atomic_i128_aligned_seq_cst:
; -O1: ldaxp xzr, x8, [x2]
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-v8_1a.ll
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Expand Up @@ -121,7 +121,7 @@ define dso_local void @store_atomic_i128_aligned_unordered(i128 %value, ptr %ptr
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
; -O0: orr x8, x8, x11
; -O0: subs x8, x8, #0
; -O0: cmp x8, #0
;
; -O1-LABEL: store_atomic_i128_aligned_unordered:
; -O1: ldp x4, x5, [x2]
Expand All @@ -138,7 +138,7 @@ define dso_local void @store_atomic_i128_aligned_monotonic(i128 %value, ptr %ptr
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
; -O0: orr x8, x8, x11
; -O0: subs x8, x8, #0
; -O0: cmp x8, #0
;
; -O1-LABEL: store_atomic_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x2]
Expand All @@ -155,7 +155,7 @@ define dso_local void @store_atomic_i128_aligned_release(i128 %value, ptr %ptr)
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
; -O0: orr x8, x8, x11
; -O0: subs x8, x8, #0
; -O0: cmp x8, #0
;
; -O1-LABEL: store_atomic_i128_aligned_release:
; -O1: ldp x4, x5, [x2]
Expand All @@ -172,7 +172,7 @@ define dso_local void @store_atomic_i128_aligned_seq_cst(i128 %value, ptr %ptr)
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
; -O0: orr x8, x8, x11
; -O0: subs x8, x8, #0
; -O0: cmp x8, #0
;
; -O1-LABEL: store_atomic_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x2]
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-v8a.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -125,7 +125,7 @@ define dso_local void @store_atomic_i128_aligned_unordered(i128 %value, ptr %ptr
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
; -O0: orr x8, x8, x11
; -O0: subs x8, x8, #0
; -O0: cmp x8, #0
;
; -O1-LABEL: store_atomic_i128_aligned_unordered:
; -O1: ldxp xzr, x8, [x2]
Expand All @@ -144,7 +144,7 @@ define dso_local void @store_atomic_i128_aligned_monotonic(i128 %value, ptr %ptr
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
; -O0: orr x8, x8, x11
; -O0: subs x8, x8, #0
; -O0: cmp x8, #0
;
; -O1-LABEL: store_atomic_i128_aligned_monotonic:
; -O1: ldxp xzr, x8, [x2]
Expand All @@ -163,7 +163,7 @@ define dso_local void @store_atomic_i128_aligned_release(i128 %value, ptr %ptr)
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
; -O0: orr x8, x8, x11
; -O0: subs x8, x8, #0
; -O0: cmp x8, #0
;
; -O1-LABEL: store_atomic_i128_aligned_release:
; -O1: ldxp xzr, x8, [x2]
Expand All @@ -182,7 +182,7 @@ define dso_local void @store_atomic_i128_aligned_seq_cst(i128 %value, ptr %ptr)
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
; -O0: orr x8, x8, x11
; -O0: subs x8, x8, #0
; -O0: cmp x8, #0
;
; -O1-LABEL: store_atomic_i128_aligned_seq_cst:
; -O1: ldaxp xzr, x8, [x2]
Expand Down
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