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[NVPTX] Rename register classes after float register removal (NFC) #145255

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Merged
AlexMaclean merged 1 commit into from
Jun 23, 2025
Merged

[NVPTX] Rename register classes after float register removal (NFC) #145255

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10 changes: 5 additions & 5 deletions llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -215,15 +215,15 @@ unsigned NVPTXAsmPrinter::encodeVirtualRegister(unsigned Reg) {
// Encode the register class in the upper 4 bits
// Must be kept in sync with NVPTXInstPrinter::printRegName
unsigned Ret = 0;
if (RC == &NVPTX::Int1RegsRegClass) {
if (RC == &NVPTX::B1RegClass) {
Ret = (1 << 28);
} else if (RC == &NVPTX::Int16RegsRegClass) {
} else if (RC == &NVPTX::B16RegClass) {
Ret = (2 << 28);
} else if (RC == &NVPTX::Int32RegsRegClass) {
} else if (RC == &NVPTX::B32RegClass) {
Ret = (3 << 28);
} else if (RC == &NVPTX::Int64RegsRegClass) {
} else if (RC == &NVPTX::B64RegClass) {
Ret = (4 << 28);
} else if (RC == &NVPTX::Int128RegsRegClass) {
} else if (RC == &NVPTX::B128RegClass) {
Ret = (7 << 28);
} else {
report_fatal_error("Bad register class");
Expand Down
34 changes: 17 additions & 17 deletions llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -589,18 +589,18 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
setOperationAction(Op, VT, IsOpSupported ? Action : NoI16x2Action);
};

addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
addRegisterClass(MVT::v2i16, &NVPTX::Int32RegsRegClass);
addRegisterClass(MVT::v4i8, &NVPTX::Int32RegsRegClass);
addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
addRegisterClass(MVT::f32, &NVPTX::Int32RegsRegClass);
addRegisterClass(MVT::f64, &NVPTX::Int64RegsRegClass);
addRegisterClass(MVT::f16, &NVPTX::Int16RegsRegClass);
addRegisterClass(MVT::v2f16, &NVPTX::Int32RegsRegClass);
addRegisterClass(MVT::bf16, &NVPTX::Int16RegsRegClass);
addRegisterClass(MVT::v2bf16, &NVPTX::Int32RegsRegClass);
addRegisterClass(MVT::i1, &NVPTX::B1RegClass);
addRegisterClass(MVT::i16, &NVPTX::B16RegClass);
addRegisterClass(MVT::v2i16, &NVPTX::B32RegClass);
addRegisterClass(MVT::v4i8, &NVPTX::B32RegClass);
addRegisterClass(MVT::i32, &NVPTX::B32RegClass);
addRegisterClass(MVT::i64, &NVPTX::B64RegClass);
addRegisterClass(MVT::f32, &NVPTX::B32RegClass);
addRegisterClass(MVT::f64, &NVPTX::B64RegClass);
addRegisterClass(MVT::f16, &NVPTX::B16RegClass);
addRegisterClass(MVT::v2f16, &NVPTX::B32RegClass);
addRegisterClass(MVT::bf16, &NVPTX::B16RegClass);
addRegisterClass(MVT::v2bf16, &NVPTX::B32RegClass);

// Conversion to/from FP16/FP16x2 is always legal.
setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
Expand Down Expand Up @@ -4866,22 +4866,22 @@ NVPTXTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'b':
return std::make_pair(0U, &NVPTX::Int1RegsRegClass);
return std::make_pair(0U, &NVPTX::B1RegClass);
case 'c':
case 'h':
return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
return std::make_pair(0U, &NVPTX::B16RegClass);
case 'r':
case 'f':
return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
return std::make_pair(0U, &NVPTX::B32RegClass);
case 'l':
case 'N':
case 'd':
return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
return std::make_pair(0U, &NVPTX::B64RegClass);
case 'q': {
if (STI.getSmVersion() < 70)
report_fatal_error("Inline asm with 128 bit operands is only "
"supported for sm_70 and higher!");
return std::make_pair(0U, &NVPTX::Int128RegsRegClass);
return std::make_pair(0U, &NVPTX::B128RegClass);
}
}
}
Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -39,15 +39,15 @@ void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
report_fatal_error("Copy one register into another with a different width");

unsigned Op;
if (DestRC == &NVPTX::Int1RegsRegClass) {
if (DestRC == &NVPTX::B1RegClass) {
Op = NVPTX::IMOV1r;
} else if (DestRC == &NVPTX::Int16RegsRegClass) {
} else if (DestRC == &NVPTX::B16RegClass) {
Op = NVPTX::MOV16r;
} else if (DestRC == &NVPTX::Int32RegsRegClass) {
} else if (DestRC == &NVPTX::B32RegClass) {
Op = NVPTX::IMOV32r;
} else if (DestRC == &NVPTX::Int64RegsRegClass) {
} else if (DestRC == &NVPTX::B64RegClass) {
Op = NVPTX::IMOV64r;
} else if (DestRC == &NVPTX::Int128RegsRegClass) {
} else if (DestRC == &NVPTX::B128RegClass) {
Op = NVPTX::IMOV128r;
} else {
llvm_unreachable("Bad register copy");
Expand Down
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