[WebAssembly] [Backend] Wasm optimize illegal bitmask #145627
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@lukel97 hi Luke! just tagging you in just in case you find it interesting |
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i'm finding out that in web assembly, in llvm ir, v64i8 can be converted to 4 v128 as input to the selection dag, but v64i4 will degenerate to 64 integers of i32. I'm not sure how to handle this case so that v64i4 can be converted to 2 v128? I set it via WebAssembly::getPreferredVectorAction so that if (EltVT == MVT::v64i4) return TypeSplitVector; the only place that calls this function in TargetLoweringBase is computeRegisterProperties. The enum fall throughs to TypeScalarizeVector (below is the block for it in computeRegisterProperties), but after this i'm not sure where to go next The llvm ir test case is hand written (not generated from a C file) so im not sure how applicable the optimization will be. Extra discussion needed |
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@llvm/pr-subscribers-backend-webassembly Author: jjasmine (badumbatish) ChangesDraft pull request for #131980. Currently, the case for illegal bitmask (v32i8 or v64i8) is that at the SelectionDag level, two (four) vectors of v128 will be concatenated together, then they'll all be SETCC by the same pseudo illegal instruction, which requires expansion later on. I opt for SETCC-ing them seperately, bitcast and zext them and then add them up together in the end. I will review my code again tomorrow one more time before undrafting. Patch is 31.85 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/145627.diff 2 Files Affected:
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 3cd923c0ba058..bfc961df95dc8 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -18,12 +18,14 @@
#include "WebAssemblySubtarget.h"
#include "WebAssemblyTargetMachine.h"
#include "WebAssemblyUtilities.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SDPatternMatch.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/IR/DiagnosticInfo.h"
@@ -3214,20 +3216,26 @@ static SDValue performTruncateCombine(SDNode *N,
static SDValue performBitcastCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI) {
+ using namespace llvm::SDPatternMatch;
auto &DAG = DCI.DAG;
SDLoc DL(N);
SDValue Src = N->getOperand(0);
EVT VT = N->getValueType(0);
EVT SrcVT = Src.getValueType();
- // bitcast <N x i1> to iN
+ bool Vectorizable = DCI.isBeforeLegalize() && VT.isScalarInteger() &&
+ SrcVT.isFixedLengthVector() &&
+ SrcVT.getScalarType() == MVT::i1;
+
+ if (!Vectorizable)
+ return SDValue();
+
+ unsigned NumElts = SrcVT.getVectorNumElements();
+ EVT Width = MVT::getIntegerVT(128 / NumElts);
+
+ // bitcast <N x i1> to iN, where N = 2, 4, 8, 16 (legal)
// ==> bitmask
- if (DCI.isBeforeLegalize() && VT.isScalarInteger() &&
- SrcVT.isFixedLengthVector() && SrcVT.getScalarType() == MVT::i1) {
- unsigned NumElts = SrcVT.getVectorNumElements();
- if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
- return SDValue();
- EVT Width = MVT::getIntegerVT(128 / NumElts);
+ if (NumElts == 2 || NumElts == 4 || NumElts == 8 || NumElts == 16) {
return DAG.getZExtOrTrunc(
DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
{DAG.getConstant(Intrinsic::wasm_bitmask, DL, MVT::i32),
@@ -3236,6 +3244,57 @@ static SDValue performBitcastCombine(SDNode *N,
DL, VT);
}
+ // bitcast <N x i1>(setcc ...) to concat iN, where N = 32 and 64 (illegal)
+ if (NumElts == 32 || NumElts == 64) {
+ // Strategy: We will setcc them seperately in v16i1
+ // Bitcast them to i16, extend them to either i32 or i64.
+ // Add them together, shifting left 1 by 1.
+ SDValue Concat, SetCCVector;
+ ISD::CondCode SetCond;
+
+ if (!sd_match(N, m_BitCast(m_c_SetCC(m_Value(Concat),
+ m_VectorVT(m_Value(SetCCVector)),
+ m_CondCode(SetCond)))))
+ return SDValue();
+ // COMMITTED at this point, SDValue() if match fails.
+ if (Concat.getOpcode() != ISD::CONCAT_VECTORS)
+ return SDValue();
+ // CHECK IF VECTOR is a constant, i.e all values are the same
+ if (!ISD::isBuildVectorOfConstantSDNodes(SetCCVector.getNode()))
+ return SDValue();
+
+ SmallVector<SDValue> Vec;
+ for (SDValue Const : SetCCVector->ops()) {
+ Vec.push_back(Const);
+ if (Vec.size() >= 16)
+ break;
+ }
+
+ // Build our own version of splat Vector.
+ SDValue SplitSetCCVec = DAG.getBuildVector(MVT::v16i8, DL, Vec);
+
+ SmallVector<SDValue> VectorsToShuffle;
+ for (SDValue V : Concat->ops())
+ VectorsToShuffle.push_back(DAG.getBitcast(
+ MVT::i16, DAG.getSetCC(DL, MVT::v16i1, V, SplitSetCCVec, SetCond)));
+
+ MVT ReturnType = VectorsToShuffle.size() == 2 ? MVT::i32 : MVT::i64;
+ SDValue ReturningInteger = DAG.getConstant(0, DL, ReturnType);
+
+ for (SDValue V : VectorsToShuffle) {
+ ReturningInteger = DAG.getNode(
+ ISD::SHL, DL, ReturnType,
+ {DAG.getShiftAmountConstant(16, ReturnType, DL), ReturningInteger});
+
+ SDValue ExtendedV = DAG.getZExtOrTrunc(V, DL, ReturnType);
+ ReturningInteger =
+ DAG.getNode(ISD::ADD, DL, ReturnType, {ReturningInteger, ExtendedV});
+ }
+
+ // ReturningInteger->print(llvm::errs());
+ return ReturningInteger;
+ }
+
return SDValue();
}
diff --git a/llvm/test/CodeGen/WebAssembly/simd-illegal-bitmask.ll b/llvm/test/CodeGen/WebAssembly/simd-illegal-bitmask.ll
new file mode 100644
index 0000000000000..58152afbfcb5a
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/simd-illegal-bitmask.ll
@@ -0,0 +1,548 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -O3 -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
+
+
+target triple = "wasm64"
+
+
+define i16 @legal_bitcast_v16i8(<16 x i8> %x) {
+; CHECK-LABEL: legal_bitcast_v16i8:
+; CHECK: .functype legal_bitcast_v16i8 (v128) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: v128.const $push0=, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
+; CHECK-NEXT: i8x16.eq $push1=, $0, $pop0
+; CHECK-NEXT: i8x16.bitmask $push2=, $pop1
+; CHECK-NEXT: return $pop2
+ %z = icmp eq <16 x i8> %x, splat (i8 16)
+ %res = bitcast <16 x i1> %z to i16
+ ret i16 %res
+}
+
+define i32 @optimize_illegal_bitcast_v32i8(<32 x i8> %x) {
+; CHECK-LABEL: optimize_illegal_bitcast_v32i8:
+; CHECK: .functype optimize_illegal_bitcast_v32i8 (v128, v128) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push2=, 16
+; CHECK-NEXT: v128.const $push10=, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32
+; CHECK-NEXT: local.tee $push9=, $2=, $pop10
+; CHECK-NEXT: i8x16.eq $push0=, $0, $pop9
+; CHECK-NEXT: i8x16.bitmask $push1=, $pop0
+; CHECK-NEXT: i32.const $push8=, 16
+; CHECK-NEXT: i32.add $push3=, $pop1, $pop8
+; CHECK-NEXT: i32.shl $push4=, $pop2, $pop3
+; CHECK-NEXT: i8x16.eq $push5=, $1, $2
+; CHECK-NEXT: i8x16.bitmask $push6=, $pop5
+; CHECK-NEXT: i32.add $push7=, $pop4, $pop6
+; CHECK-NEXT: return $pop7
+ %z = icmp eq <32 x i8> %x, splat (i8 32)
+ %res = bitcast <32 x i1> %z to i32
+ ret i32 %res
+}
+
+
+define i64 @optimize_illegal_bitcast_v64i8(<64 x i8> %x) {
+; CHECK-LABEL: optimize_illegal_bitcast_v64i8:
+; CHECK: .functype optimize_illegal_bitcast_v64i8 (v128, v128, v128, v128) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i64.const $push3=, 16
+; CHECK-NEXT: i64.const $push24=, 16
+; CHECK-NEXT: i64.const $push23=, 16
+; CHECK-NEXT: v128.const $push22=, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64
+; CHECK-NEXT: local.tee $push21=, $4=, $pop22
+; CHECK-NEXT: i8x16.eq $push0=, $0, $pop21
+; CHECK-NEXT: i8x16.bitmask $push1=, $pop0
+; CHECK-NEXT: i64.extend_i32_u $push2=, $pop1
+; CHECK-NEXT: i64.const $push20=, 16
+; CHECK-NEXT: i64.add $push4=, $pop2, $pop20
+; CHECK-NEXT: i64.shl $push5=, $pop23, $pop4
+; CHECK-NEXT: i8x16.eq $push6=, $1, $4
+; CHECK-NEXT: i8x16.bitmask $push7=, $pop6
+; CHECK-NEXT: i64.extend_i32_u $push8=, $pop7
+; CHECK-NEXT: i64.add $push9=, $pop5, $pop8
+; CHECK-NEXT: i64.shl $push10=, $pop24, $pop9
+; CHECK-NEXT: i8x16.eq $push11=, $2, $4
+; CHECK-NEXT: i8x16.bitmask $push12=, $pop11
+; CHECK-NEXT: i64.extend_i32_u $push13=, $pop12
+; CHECK-NEXT: i64.add $push14=, $pop10, $pop13
+; CHECK-NEXT: i64.shl $push15=, $pop3, $pop14
+; CHECK-NEXT: i8x16.eq $push16=, $3, $4
+; CHECK-NEXT: i8x16.bitmask $push17=, $pop16
+; CHECK-NEXT: i64.extend_i32_u $push18=, $pop17
+; CHECK-NEXT: i64.add $push19=, $pop15, $pop18
+; CHECK-NEXT: return $pop19
+ %z = icmp eq <64 x i8> %x, splat (i8 64)
+ %res = bitcast <64 x i1> %z to i64
+ ret i64 %res
+}
+
+define i64 @optimize_illegal_bitcast_v64i4(<64 x i4> %x) {
+; CHECK-LABEL: optimize_illegal_bitcast_v64i4:
+; CHECK: .functype optimize_illegal_bitcast_v64i4 (i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: global.get $push355=, __stack_pointer
+; CHECK-NEXT: i64.const $push356=, 16
+; CHECK-NEXT: i64.sub $drop=, $pop355, $pop356
+; CHECK-NEXT: i8x16.splat $push273=, $0
+; CHECK-NEXT: i8x16.replace_lane $push274=, $pop273, 1, $1
+; CHECK-NEXT: i8x16.replace_lane $push275=, $pop274, 2, $2
+; CHECK-NEXT: i8x16.replace_lane $push276=, $pop275, 3, $3
+; CHECK-NEXT: i8x16.replace_lane $push277=, $pop276, 4, $4
+; CHECK-NEXT: i8x16.replace_lane $push278=, $pop277, 5, $5
+; CHECK-NEXT: i8x16.replace_lane $push279=, $pop278, 6, $6
+; CHECK-NEXT: i8x16.replace_lane $push280=, $pop279, 7, $7
+; CHECK-NEXT: i8x16.replace_lane $push281=, $pop280, 8, $8
+; CHECK-NEXT: i8x16.replace_lane $push282=, $pop281, 9, $9
+; CHECK-NEXT: i8x16.replace_lane $push283=, $pop282, 10, $10
+; CHECK-NEXT: i8x16.replace_lane $push284=, $pop283, 11, $11
+; CHECK-NEXT: i8x16.replace_lane $push285=, $pop284, 12, $12
+; CHECK-NEXT: i8x16.replace_lane $push286=, $pop285, 13, $13
+; CHECK-NEXT: i8x16.replace_lane $push287=, $pop286, 14, $14
+; CHECK-NEXT: i8x16.replace_lane $push288=, $pop287, 15, $15
+; CHECK-NEXT: v128.const $push460=, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15
+; CHECK-NEXT: local.tee $push459=, $64=, $pop460
+; CHECK-NEXT: v128.and $push289=, $pop288, $pop459
+; CHECK-NEXT: v128.const $push458=, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT: local.tee $push457=, $65=, $pop458
+; CHECK-NEXT: i8x16.eq $push456=, $pop289, $pop457
+; CHECK-NEXT: local.tee $push455=, $66=, $pop456
+; CHECK-NEXT: i8x16.extract_lane_u $push290=, $pop455, 0
+; CHECK-NEXT: i32.const $push18=, 1
+; CHECK-NEXT: i32.and $push291=, $pop290, $pop18
+; CHECK-NEXT: i8x16.extract_lane_u $push292=, $66, 1
+; CHECK-NEXT: i32.const $push454=, 1
+; CHECK-NEXT: i32.and $push293=, $pop292, $pop454
+; CHECK-NEXT: i32.const $push453=, 1
+; CHECK-NEXT: i32.shl $push294=, $pop293, $pop453
+; CHECK-NEXT: i32.or $push295=, $pop291, $pop294
+; CHECK-NEXT: i8x16.extract_lane_u $push296=, $66, 2
+; CHECK-NEXT: i32.const $push452=, 1
+; CHECK-NEXT: i32.and $push297=, $pop296, $pop452
+; CHECK-NEXT: i32.const $push121=, 2
+; CHECK-NEXT: i32.shl $push298=, $pop297, $pop121
+; CHECK-NEXT: i32.or $push299=, $pop295, $pop298
+; CHECK-NEXT: i8x16.extract_lane_u $push300=, $66, 3
+; CHECK-NEXT: i32.const $push451=, 1
+; CHECK-NEXT: i32.and $push301=, $pop300, $pop451
+; CHECK-NEXT: i32.const $push126=, 3
+; CHECK-NEXT: i32.shl $push302=, $pop301, $pop126
+; CHECK-NEXT: i32.or $push303=, $pop299, $pop302
+; CHECK-NEXT: i8x16.extract_lane_u $push304=, $66, 4
+; CHECK-NEXT: i32.const $push450=, 1
+; CHECK-NEXT: i32.and $push305=, $pop304, $pop450
+; CHECK-NEXT: i32.const $push131=, 4
+; CHECK-NEXT: i32.shl $push306=, $pop305, $pop131
+; CHECK-NEXT: i32.or $push307=, $pop303, $pop306
+; CHECK-NEXT: i8x16.extract_lane_u $push308=, $66, 5
+; CHECK-NEXT: i32.const $push449=, 1
+; CHECK-NEXT: i32.and $push309=, $pop308, $pop449
+; CHECK-NEXT: i32.const $push136=, 5
+; CHECK-NEXT: i32.shl $push310=, $pop309, $pop136
+; CHECK-NEXT: i32.or $push311=, $pop307, $pop310
+; CHECK-NEXT: i8x16.extract_lane_u $push312=, $66, 6
+; CHECK-NEXT: i32.const $push448=, 1
+; CHECK-NEXT: i32.and $push313=, $pop312, $pop448
+; CHECK-NEXT: i32.const $push141=, 6
+; CHECK-NEXT: i32.shl $push314=, $pop313, $pop141
+; CHECK-NEXT: i32.or $push315=, $pop311, $pop314
+; CHECK-NEXT: i8x16.extract_lane_u $push316=, $66, 7
+; CHECK-NEXT: i32.const $push447=, 1
+; CHECK-NEXT: i32.and $push317=, $pop316, $pop447
+; CHECK-NEXT: i32.const $push146=, 7
+; CHECK-NEXT: i32.shl $push318=, $pop317, $pop146
+; CHECK-NEXT: i32.or $push319=, $pop315, $pop318
+; CHECK-NEXT: i8x16.extract_lane_u $push320=, $66, 8
+; CHECK-NEXT: i32.const $push446=, 1
+; CHECK-NEXT: i32.and $push321=, $pop320, $pop446
+; CHECK-NEXT: i32.const $push151=, 8
+; CHECK-NEXT: i32.shl $push322=, $pop321, $pop151
+; CHECK-NEXT: i32.or $push323=, $pop319, $pop322
+; CHECK-NEXT: i8x16.extract_lane_u $push324=, $66, 9
+; CHECK-NEXT: i32.const $push445=, 1
+; CHECK-NEXT: i32.and $push325=, $pop324, $pop445
+; CHECK-NEXT: i32.const $push156=, 9
+; CHECK-NEXT: i32.shl $push326=, $pop325, $pop156
+; CHECK-NEXT: i32.or $push327=, $pop323, $pop326
+; CHECK-NEXT: i8x16.extract_lane_u $push328=, $66, 10
+; CHECK-NEXT: i32.const $push444=, 1
+; CHECK-NEXT: i32.and $push329=, $pop328, $pop444
+; CHECK-NEXT: i32.const $push161=, 10
+; CHECK-NEXT: i32.shl $push330=, $pop329, $pop161
+; CHECK-NEXT: i32.or $push331=, $pop327, $pop330
+; CHECK-NEXT: i8x16.extract_lane_u $push332=, $66, 11
+; CHECK-NEXT: i32.const $push443=, 1
+; CHECK-NEXT: i32.and $push333=, $pop332, $pop443
+; CHECK-NEXT: i32.const $push166=, 11
+; CHECK-NEXT: i32.shl $push334=, $pop333, $pop166
+; CHECK-NEXT: i32.or $push335=, $pop331, $pop334
+; CHECK-NEXT: i8x16.extract_lane_u $push336=, $66, 12
+; CHECK-NEXT: i32.const $push442=, 1
+; CHECK-NEXT: i32.and $push337=, $pop336, $pop442
+; CHECK-NEXT: i32.const $push171=, 12
+; CHECK-NEXT: i32.shl $push338=, $pop337, $pop171
+; CHECK-NEXT: i32.or $push339=, $pop335, $pop338
+; CHECK-NEXT: i8x16.extract_lane_u $push340=, $66, 13
+; CHECK-NEXT: i32.const $push441=, 1
+; CHECK-NEXT: i32.and $push341=, $pop340, $pop441
+; CHECK-NEXT: i32.const $push176=, 13
+; CHECK-NEXT: i32.shl $push342=, $pop341, $pop176
+; CHECK-NEXT: i32.or $push343=, $pop339, $pop342
+; CHECK-NEXT: i8x16.extract_lane_u $push344=, $66, 14
+; CHECK-NEXT: i32.const $push440=, 1
+; CHECK-NEXT: i32.and $push345=, $pop344, $pop440
+; CHECK-NEXT: i32.const $push181=, 14
+; CHECK-NEXT: i32.shl $push346=, $pop345, $pop181
+; CHECK-NEXT: i32.or $push347=, $pop343, $pop346
+; CHECK-NEXT: i8x16.extract_lane_u $push348=, $66, 15
+; CHECK-NEXT: i32.const $push185=, 15
+; CHECK-NEXT: i32.shl $push349=, $pop348, $pop185
+; CHECK-NEXT: i32.or $push350=, $pop347, $pop349
+; CHECK-NEXT: i32.const $push188=, 65535
+; CHECK-NEXT: i32.and $push351=, $pop350, $pop188
+; CHECK-NEXT: i8x16.splat $push194=, $16
+; CHECK-NEXT: i8x16.replace_lane $push195=, $pop194, 1, $17
+; CHECK-NEXT: i8x16.replace_lane $push196=, $pop195, 2, $18
+; CHECK-NEXT: i8x16.replace_lane $push197=, $pop196, 3, $19
+; CHECK-NEXT: i8x16.replace_lane $push198=, $pop197, 4, $20
+; CHECK-NEXT: i8x16.replace_lane $push199=, $pop198, 5, $21
+; CHECK-NEXT: i8x16.replace_lane $push200=, $pop199, 6, $22
+; CHECK-NEXT: i8x16.replace_lane $push201=, $pop200, 7, $23
+; CHECK-NEXT: i8x16.replace_lane $push202=, $pop201, 8, $24
+; CHECK-NEXT: i8x16.replace_lane $push203=, $pop202, 9, $25
+; CHECK-NEXT: i8x16.replace_lane $push204=, $pop203, 10, $26
+; CHECK-NEXT: i8x16.replace_lane $push205=, $pop204, 11, $27
+; CHECK-NEXT: i8x16.replace_lane $push206=, $pop205, 12, $28
+; CHECK-NEXT: i8x16.replace_lane $push207=, $pop206, 13, $29
+; CHECK-NEXT: i8x16.replace_lane $push208=, $pop207, 14, $30
+; CHECK-NEXT: i8x16.replace_lane $push209=, $pop208, 15, $31
+; CHECK-NEXT: v128.and $push210=, $pop209, $64
+; CHECK-NEXT: i8x16.eq $push439=, $pop210, $65
+; CHECK-NEXT: local.tee $push438=, $66=, $pop439
+; CHECK-NEXT: i8x16.extract_lane_u $push270=, $pop438, 15
+; CHECK-NEXT: i32.const $push93=, 31
+; CHECK-NEXT: i32.shl $push271=, $pop270, $pop93
+; CHECK-NEXT: i8x16.extract_lane_u $push266=, $66, 14
+; CHECK-NEXT: i32.const $push437=, 1
+; CHECK-NEXT: i32.and $push267=, $pop266, $pop437
+; CHECK-NEXT: i32.const $push89=, 30
+; CHECK-NEXT: i32.shl $push268=, $pop267, $pop89
+; CHECK-NEXT: i8x16.extract_lane_u $push262=, $66, 13
+; CHECK-NEXT: i32.const $push436=, 1
+; CHECK-NEXT: i32.and $push263=, $pop262, $pop436
+; CHECK-NEXT: i32.const $push84=, 29
+; CHECK-NEXT: i32.shl $push264=, $pop263, $pop84
+; CHECK-NEXT: i8x16.extract_lane_u $push258=, $66, 12
+; CHECK-NEXT: i32.const $push435=, 1
+; CHECK-NEXT: i32.and $push259=, $pop258, $pop435
+; CHECK-NEXT: i32.const $push79=, 28
+; CHECK-NEXT: i32.shl $push260=, $pop259, $pop79
+; CHECK-NEXT: i8x16.extract_lane_u $push254=, $66, 11
+; CHECK-NEXT: i32.const $push434=, 1
+; CHECK-NEXT: i32.and $push255=, $pop254, $pop434
+; CHECK-NEXT: i32.const $push74=, 27
+; CHECK-NEXT: i32.shl $push256=, $pop255, $pop74
+; CHECK-NEXT: i8x16.extract_lane_u $push250=, $66, 10
+; CHECK-NEXT: i32.const $push433=, 1
+; CHECK-NEXT: i32.and $push251=, $pop250, $pop433
+; CHECK-NEXT: i32.const $push69=, 26
+; CHECK-NEXT: i32.shl $push252=, $pop251, $pop69
+; CHECK-NEXT: i8x16.extract_lane_u $push246=, $66, 9
+; CHECK-NEXT: i32.const $push432=, 1
+; CHECK-NEXT: i32.and $push247=, $pop246, $pop432
+; CHECK-NEXT: i32.const $push64=, 25
+; CHECK-NEXT: i32.shl $push248=, $pop247, $pop64
+; CHECK-NEXT: i8x16.extract_lane_u $push242=, $66, 8
+; CHECK-NEXT: i32.const $push431=, 1
+; CHECK-NEXT: i32.and $push243=, $pop242, $pop431
+; CHECK-NEXT: i32.const $push59=, 24
+; CHECK-NEXT: i32.shl $push244=, $pop243, $pop59
+; CHECK-NEXT: i8x16.extract_lane_u $push238=, $66, 7
+; CHECK-NEXT: i32.const $push430=, 1
+; CHECK-NEXT: i32.and $push239=, $pop238, $pop430
+; CHECK-NEXT: i32.const $push54=, 23
+; CHECK-NEXT: i32.shl $push240=, $pop239, $pop54
+; CHECK-NEXT: i8x16.extract_lane_u $push234=, $66, 6
+; CHECK-NEXT: i32.const $push429=, 1
+; CHECK-NEXT: i32.and $push235=, $pop234, $pop429
+; CHECK-NEXT: i32.const $push49=, 22
+; CHECK-NEXT: i32.shl $push236=, $pop235, $pop49
+; CHECK-NEXT: i8x16.extract_lane_u $push230=, $66, 5
+; CHECK-NEXT: i32.const $push428=, 1
+; CHECK-NEXT: i32.and $push231=, $pop230, $pop428
+; CHECK-NEXT: i32.const $push44=, 21
+; CHECK-NEXT: i32.shl $push232=, $pop231, $pop44
+; CHECK-NEXT: i8x16.extract_lane_u $push226=, $66, 4
+; CHECK-NEXT: i32.const $push427=, 1
+; CHECK-NEXT: i32.and $push227=, $pop226, $pop427
+; CHECK-NEXT: i32.const $push39=, 20
+; CHECK-NEXT: i32.shl $push228=, $pop227, $pop39
+; CHECK-NEXT: i8x16.extract_lane_u $push222=, $66, 3
+; CHECK-NEXT: i32.const $push426=, 1
+; CHECK-NEXT: i32.and $push223=, $pop222, $pop426
+; CHECK-NEXT: i32.const $push34=, 19
+; CHECK-NEXT: i32.shl $push224=, $pop223, $pop34
+; CHECK-NEXT: i8x16.extract_lane_u $push218=, $66, 2
+; CHECK-NEXT: i32.const $push425=, 1
+; CHECK-NEXT: i32.and $push219=, $pop218, $pop425
+; CHECK-NEXT: i32.const $push29=, 18
+; CHECK-NEXT: i32.shl $push220=, $pop219, $pop29
+; CHECK-NEXT: i8x16.extract_lane_u $push214=, $66, 1
+; CHECK-NEXT: i32.const $push424=, 1
+; CHECK-NEXT: i32.and $push215=, $pop214, $pop424
+; CHECK-NEXT: i32.const $push24=, 17
+; CHECK-NEXT: i32.shl $push216=, $pop215, $pop24
+; CHECK-NEXT: i8x16.extract_lane_u $push211=, $66, 0
+; CHECK-NEXT: i32.const $push423=, 1
+; CHECK-NEXT: i32.and $push212=, $pop211, $pop423
+; CHECK-NEXT: i32.const $push20=, 16
+; CHECK-NEXT: i32.shl $push213=, $pop212, $pop20
+; CHECK-NEXT: i32.or $push217=, $pop216, $pop213
+; CHECK-NEXT: i32.or $push221=, $pop220, $pop217
+; CHECK-NEXT: i32.or $push225=, $pop224, $pop221
+; CHECK-NEXT: i32.or $push229=, $pop228, $pop225
+; CHECK-NEXT: i32.or $push233=, $pop232, $pop229
+; CHECK-NEXT: i32.or $push237=, $pop236, $pop233
+; CHECK-NEXT: i32.or $push241=, $pop240, $pop237
+; CHECK-NEXT: i32.or $push245=, $pop244, $pop241
+; CHECK-NEXT: i32.or $push249=, $pop248, $pop245
+; CHECK-NEXT: i32.or $push253=, $pop252, $pop249
+; CHECK-NEXT: i32.or $push257=, $pop256, $pop253
+; CHECK-NEXT: i32.or $push261=, $pop260, $pop257
+; CHECK-NEXT: i32.or...
[truncated]
|
Contributor
Author
|
@sparker-arm hi there! i'm not sure who to tag for this issue I'm having, but would it be possible for a <64 x i4> to be converted to 2 v128 since <64 x i8> can be converted to 4 v128? Right now without converting to v128, the assembly degenerates to about 400 lines. If its possible to convert <64 x i4> to 2 v128, I'd appreciate some pointers or some directions on where to proceed next |
Contributor
|
Out of curiosity, are there any languages, or frameworks, compiling to wasm that will use an i4? Either way, I think it would be okay, and easier to review, if i4 support came in a separate patch. |
sparker-arm
reviewed
Jun 27, 2025
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hmm not that i know of. The llvm ir snippet that has <64 x i4 > is hand written by me, if needed, I can remove it if it's not applicable? |
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lukel97
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Jun 30, 2025
Add nonconst, varying vector precommit test to simd-illegal-bitmask test.
Added bitmask optimizing for illegal varying vector. Before we can only optimize const vector in setcc.
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failing random flang test here with some new warnings added, will rebase and repush |
Contributor
Author
|
thanks Derek, i don't have commit access right now. Would love for somebody to help me land the patch |
Member
|
I can do that. Can you update the OP comment with the text you want to have as the commit message? Currently it still says "draft". |
Contributor
Author
changed. Tysm! |
|
@badumbatish Congratulations on having your first Pull Request (PR) merged into the LLVM Project! Your changes will be combined with recent changes from other authors, then tested by our build bots. If there is a problem with a build, you may receive a report in an email or a comment on this PR. Please check whether problems have been caused by your change specifically, as the builds can include changes from many authors. It is not uncommon for your change to be included in a build that fails due to someone else's changes, or infrastructure issues. How to do this, and the rest of the post-merge process, is covered in detail here. If your change does cause a problem, it may be reverted, or you can revert it yourself. This is a normal part of LLVM development. You can fix your changes and open a new PR to merge them again. If you don't get any reports, no action is required from you. Your changes are working as expected, well done! |
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[WebAssembly] [Backend] Wasm optimize illegal bitmask for #131980.
Currently, the case for illegal bitmask (v32i8 or v64i8) is that at the SelectionDag level, two (four) vectors of v128 will be concatenated together, then they'll all be SETCC by the same pseudo illegal instruction, which requires expansion later on.
I opt for SETCC-ing them seperately, bitcast and zext them and then add them up together in the end.