[AMDGPU] Add GCNRPTarget to track register pressure against a target
#145765
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@llvm/pr-subscribers-backend-amdgpu Author: Lucas Ramirez (lucas-rami) ChangesThis adds the This is only NFC~ish because Patch is 61.85 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/145765.diff 4 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
index eed3fb20f5be8..7d6723a6108be 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
@@ -361,6 +361,69 @@ static LaneBitmask findUseBetween(unsigned Reg, LaneBitmask LastUseMask,
return LastUseMask;
}
+////////////////////////////////////////////////////////////////////////////////
+// GCNRPTarget
+
+GCNRPTarget::GCNRPTarget(const MachineFunction &MF, const GCNRegPressure &RP,
+ bool CombineVGPRSavings)
+ : RP(RP), CombineVGPRSavings(CombineVGPRSavings) {
+ const Function &F = MF.getFunction();
+ const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
+ setRegLimits(ST.getMaxNumSGPRs(F), ST.getMaxNumVGPRs(F), MF);
+}
+
+GCNRPTarget::GCNRPTarget(unsigned NumSGPRs, unsigned NumVGPRs,
+ const MachineFunction &MF, const GCNRegPressure &RP,
+ bool CombineVGPRSavings)
+ : RP(RP), CombineVGPRSavings(CombineVGPRSavings) {
+ setRegLimits(NumSGPRs, NumVGPRs, MF);
+}
+
+GCNRPTarget::GCNRPTarget(unsigned Occupancy, const MachineFunction &MF,
+ const GCNRegPressure &RP, bool CombineVGPRSavings)
+ : RP(RP), CombineVGPRSavings(CombineVGPRSavings) {
+ const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
+ unsigned DynamicVGPRBlockSize =
+ MF.getInfo<SIMachineFunctionInfo>()->getDynamicVGPRBlockSize();
+ setRegLimits(ST.getMaxNumSGPRs(Occupancy, /*Addressable=*/false),
+ ST.getMaxNumVGPRs(Occupancy, DynamicVGPRBlockSize), MF);
+}
+
+void GCNRPTarget::setRegLimits(unsigned NumSGPRs, unsigned NumVGPRs,
+ const MachineFunction &MF) {
+ const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
+ unsigned DynamicVGPRBlockSize =
+ MF.getInfo<SIMachineFunctionInfo>()->getDynamicVGPRBlockSize();
+ MaxSGPRs = std::min(ST.getAddressableNumSGPRs(), NumSGPRs);
+ MaxVGPRs = std::min(ST.getAddressableNumArchVGPRs(), NumVGPRs);
+ MaxUnifiedVGPRs =
+ ST.hasGFX90AInsts()
+ ? std::min(ST.getAddressableNumVGPRs(DynamicVGPRBlockSize), NumVGPRs)
+ : 0;
+}
+
+bool GCNRPTarget::isSaveBeneficial(Register Reg,
+ const MachineRegisterInfo &MRI) const {
+ const TargetRegisterClass *RC = MRI.getRegClass(Reg);
+ const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
+ const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo *>(TRI);
+
+ if (SRI->isSGPRClass(RC))
+ return RP.getSGPRNum() > MaxSGPRs;
+ unsigned NumVGPRs =
+ SRI->isAGPRClass(RC) ? RP.getAGPRNum() : RP.getArchVGPRNum();
+ return isVGPRBankSaveBeneficial(NumVGPRs);
+}
+
+bool GCNRPTarget::satisfied() const {
+ if (RP.getSGPRNum() > MaxSGPRs)
+ return false;
+ if (RP.getVGPRNum(false) > MaxVGPRs &&
+ (!CombineVGPRSavings || !satisifiesVGPRBanksTarget()))
+ return false;
+ return satisfiesUnifiedTarget();
+}
+
///////////////////////////////////////////////////////////////////////////////
// GCNRPTracker
diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.h b/llvm/lib/Target/AMDGPU/GCNRegPressure.h
index 397e891c8d806..32db3b78aaae5 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegPressure.h
+++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.h
@@ -31,9 +31,7 @@ class SlotIndex;
struct GCNRegPressure {
enum RegKind { SGPR, VGPR, AGPR, TOTAL_KINDS };
- GCNRegPressure() {
- clear();
- }
+ GCNRegPressure() { clear(); }
bool empty() const { return !Value[SGPR] && !Value[VGPR] && !Value[AGPR]; }
@@ -76,9 +74,7 @@ struct GCNRegPressure {
DynamicVGPRBlockSize));
}
- void inc(unsigned Reg,
- LaneBitmask PrevMask,
- LaneBitmask NewMask,
+ void inc(unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask,
const MachineRegisterInfo &MRI);
bool higherOccupancy(const GCNSubtarget &ST, const GCNRegPressure &O,
@@ -106,9 +102,7 @@ struct GCNRegPressure {
return std::equal(&Value[0], &Value[ValueArraySize], O.Value);
}
- bool operator!=(const GCNRegPressure &O) const {
- return !(*this == O);
- }
+ bool operator!=(const GCNRegPressure &O) const { return !(*this == O); }
GCNRegPressure &operator+=(const GCNRegPressure &RHS) {
for (unsigned I = 0; I < ValueArraySize; ++I)
@@ -134,8 +128,7 @@ struct GCNRegPressure {
static unsigned getRegKind(const TargetRegisterClass *RC,
const SIRegisterInfo *STI);
- friend GCNRegPressure max(const GCNRegPressure &P1,
- const GCNRegPressure &P2);
+ friend GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2);
friend Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST,
unsigned DynamicVGPRBlockSize);
@@ -162,6 +155,101 @@ inline GCNRegPressure operator-(const GCNRegPressure &P1,
return Diff;
}
+////////////////////////////////////////////////////////////////////////////////
+// GCNRPTarget
+
+/// Models a register pressure target, allowing to evaluate and track register
+/// savings against that target from a starting \ref GCNRegPressure.
+class GCNRPTarget {
+public:
+ /// Sets up the target such that the register pressure starting at \p RP does
+ /// not show register spilling on function \p MF (w.r.t. the function's
+ /// mininum target occupancy).
+ GCNRPTarget(const MachineFunction &MF, const GCNRegPressure &RP,
+ bool CombineVGPRSavings = false);
+
+ /// Sets up the target such that the register pressure starting at \p RP does
+ /// not use more than \p NumSGPRs SGPRs and \p NumVGPRs VGPRs on function \p
+ /// MF.
+ GCNRPTarget(unsigned NumSGPRs, unsigned NumVGPRs, const MachineFunction &MF,
+ const GCNRegPressure &RP, bool CombineVGPRSavings = false);
+
+ /// Sets up the target such that the register pressure starting at \p RP does
+ /// not prevent achieving an occupancy of at least \p Occupancy on function
+ /// \p MF.
+ GCNRPTarget(unsigned Occupancy, const MachineFunction &MF,
+ const GCNRegPressure &RP, bool CombineVGPRSavings = false);
+
+ const GCNRegPressure &getCurrentRP() const { return RP; }
+
+ void setRP(const GCNRegPressure &NewRP) { RP = NewRP; }
+
+ /// Determines whether saving virtual register \p Reg will be beneficial
+ /// towards achieving the RP target.
+ bool isSaveBeneficial(Register Reg, const MachineRegisterInfo &MRI) const;
+
+ /// Saves virtual register \p Reg with lanemask \p Mask.
+ void saveReg(Register Reg, LaneBitmask Mask, const MachineRegisterInfo &MRI) {
+ RP.inc(Reg, Mask, LaneBitmask::getNone(), MRI);
+ }
+
+ /// Whether the current RP is at or below the defined pressure target.
+ bool satisfied() const;
+
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
+ friend raw_ostream &operator<<(raw_ostream &OS, const GCNRPTarget &Target) {
+ OS << "Actual/Target: " << Target.RP.getSGPRNum() << '/' << Target.MaxSGPRs
+ << " SGPRs, " << Target.RP.getArchVGPRNum() << '/' << Target.MaxVGPRs
+ << " ArchVGPRs, " << Target.RP.getAGPRNum() << '/' << Target.MaxVGPRs
+ << " AGPRs";
+
+ if (Target.MaxUnifiedVGPRs) {
+ OS << ", " << Target.RP.getVGPRNum(true) << '/' << Target.MaxUnifiedVGPRs
+ << " VGPRs (unified)";
+ } else if (Target.CombineVGPRSavings) {
+ OS << ", " << Target.RP.getArchVGPRNum() + Target.RP.getAGPRNum() << '/'
+ << 2 * Target.MaxVGPRs << " VGPRs (combined target)";
+ }
+ return OS;
+ }
+#endif
+
+private:
+ /// Current register pressure.
+ GCNRegPressure RP;
+
+ /// Target number of SGPRs.
+ unsigned MaxSGPRs;
+ /// Target number of ArchVGPRs and AGPRs.
+ unsigned MaxVGPRs;
+ /// Target number of overall VGPRs for subtargets with unified RFs. Always 0
+ /// for subtargets with non-unified RFs.
+ unsigned MaxUnifiedVGPRs;
+ /// Whether we consider that the register allocator will be able to swap
+ /// between ArchVGPRs and AGPRs by copying them to a super register class.
+ /// Concretely, this allows savings in one of the VGPR banks to help toward
+ /// savings in the other VGPR bank.
+ bool CombineVGPRSavings;
+
+ inline bool satisifiesVGPRBanksTarget() const {
+ assert(CombineVGPRSavings && "only makes sense with combined savings");
+ return RP.getArchVGPRNum() + RP.getAGPRNum() <= 2 * MaxVGPRs;
+ }
+
+ /// Always satisified when the subtarget doesn't have a unified RF.
+ inline bool satisfiesUnifiedTarget() const {
+ return !MaxUnifiedVGPRs || RP.getVGPRNum(true) <= MaxUnifiedVGPRs;
+ }
+
+ inline bool isVGPRBankSaveBeneficial(unsigned NumVGPRs) const {
+ return NumVGPRs > MaxVGPRs || !satisfiesUnifiedTarget() ||
+ (CombineVGPRSavings && !satisifiesVGPRBanksTarget());
+ }
+
+ void setRegLimits(unsigned MaxSGPRs, unsigned MaxVGPRs,
+ const MachineFunction &MF);
+};
+
///////////////////////////////////////////////////////////////////////////////
// GCNRPTracker
@@ -197,9 +285,7 @@ class GCNRPTracker {
GCNRegPressure getPressure() const { return CurPressure; }
- decltype(LiveRegs) moveLiveRegs() {
- return std::move(LiveRegs);
- }
+ decltype(LiveRegs) moveLiveRegs() { return std::move(LiveRegs); }
};
GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS,
@@ -345,7 +431,7 @@ GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS,
/// Note: there is no entry in the map for instructions with empty live reg set
/// Complexity = O(NumVirtRegs * averageLiveRangeSegmentsPerReg * lg(R))
template <typename Range>
-DenseMap<MachineInstr*, GCNRPTracker::LiveRegSet>
+DenseMap<MachineInstr *, GCNRPTracker::LiveRegSet>
getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS) {
std::vector<SlotIndex> Indexes;
Indexes.reserve(std::distance(R.begin(), R.end()));
@@ -370,7 +456,7 @@ getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS) {
if (!LI.hasSubRanges()) {
for (auto SI : LiveIdxs)
LiveRegMap[SII.getInstructionFromIndex(SI)][Reg] =
- MRI.getMaxLaneMaskForVReg(Reg);
+ MRI.getMaxLaneMaskForVReg(Reg);
} else
for (const auto &S : LI.subranges()) {
// constrain search for subranges by indexes live at main range
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index 8aae340de791e..fce8f36d45969 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -1699,184 +1699,17 @@ bool PreRARematStage::allUsesAvailableAt(const MachineInstr *InstToRemat,
return true;
}
-namespace {
-/// Models excess register pressure in a region and tracks our progress as we
-/// identify rematerialization opportunities.
-struct ExcessRP {
- /// Number of excess SGPRs.
- unsigned SGPRs = 0;
- /// Number of excess ArchVGPRs.
- unsigned ArchVGPRs = 0;
- /// Number of excess AGPRs.
- unsigned AGPRs = 0;
- /// For unified register files, number of excess VGPRs. 0 otherwise.
- unsigned VGPRs = 0;
- /// For unified register files with AGPR usage, number of excess ArchVGPRs to
- /// save before we are able to save a whole allocation granule.
- unsigned ArchVGPRsToAlignment = 0;
- /// Whether the region uses AGPRs.
- bool HasAGPRs = false;
- /// Whether the subtarget has a unified RF.
- bool UnifiedRF;
- /// Whether we consider that the register allocator will be able to swap
- /// between ArchVGPRs and AGPRs by copying them to a super register class.
- /// Concretely, this allows savings of one kind of VGPR to help toward savings
- /// the other kind of VGPR.
- bool CombineVGPRSavings;
-
- /// Constructs the excess RP model; determines the excess pressure w.r.t. a
- /// maximum number of allowed SGPRs/VGPRs.
- ExcessRP(const GCNSubtarget &ST, const GCNRegPressure &RP, unsigned MaxSGPRs,
- unsigned MaxVGPRs, bool CombineVGPRSavings);
-
- /// Accounts for \p NumRegs saved SGPRs in the model. Returns whether saving
- /// these SGPRs helped reduce excess pressure.
- bool saveSGPRs(unsigned NumRegs) { return saveRegs(SGPRs, NumRegs); }
-
- /// Accounts for \p NumRegs saved ArchVGPRs in the model. Returns whether
- /// saving these ArchGPRs helped reduce excess pressure.
- bool saveArchVGPRs(unsigned NumRegs);
-
- /// Accounts for \p NumRegs saved AGPRs in the model. Returns whether saving
- /// these AGPRs helped reduce excess pressure.
- bool saveAGPRs(unsigned NumRegs);
-
- /// Returns whether there is any excess register pressure.
- operator bool() const { return SGPRs || ArchVGPRs || AGPRs || VGPRs; }
-
-#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
- friend raw_ostream &operator<<(raw_ostream &OS, const ExcessRP &Excess) {
- OS << Excess.SGPRs << " SGPRs, " << Excess.ArchVGPRs << " ArchVGPRs, and "
- << Excess.AGPRs << " AGPRs, (" << Excess.VGPRs
- << " VGPRs in total, next ArchVGPR aligment in "
- << Excess.ArchVGPRsToAlignment << " registers)\n";
- return OS;
- }
-#endif
-
-private:
- static inline bool saveRegs(unsigned &LeftToSave, unsigned &NumRegs) {
- unsigned NumSaved = std::min(LeftToSave, NumRegs);
- NumRegs -= NumSaved;
- LeftToSave -= NumSaved;
- return NumSaved;
- }
-};
-} // namespace
-
-ExcessRP::ExcessRP(const GCNSubtarget &ST, const GCNRegPressure &RP,
- unsigned MaxSGPRs, unsigned MaxVGPRs,
- bool CombineVGPRSavings)
- : UnifiedRF(ST.hasGFX90AInsts()), CombineVGPRSavings(CombineVGPRSavings) {
- // Compute excess SGPR pressure.
- unsigned NumSGPRs = RP.getSGPRNum();
- if (NumSGPRs > MaxSGPRs)
- SGPRs = NumSGPRs - MaxSGPRs;
-
- // Compute excess ArchVGPR/AGPR pressure.
- unsigned NumArchVGPRs = RP.getArchVGPRNum();
- unsigned NumAGPRs = RP.getAGPRNum();
- HasAGPRs = NumAGPRs;
- if (!UnifiedRF) {
- // Non-unified RF. Account for excess pressure for ArchVGPRs and AGPRs
- // independently.
- if (NumArchVGPRs > MaxVGPRs)
- ArchVGPRs = NumArchVGPRs - MaxVGPRs;
- if (NumAGPRs > MaxVGPRs)
- AGPRs = NumAGPRs - MaxVGPRs;
- return;
- }
-
- // Independently of whether overall VGPR pressure is under the limit, we still
- // have to check whether ArchVGPR pressure or AGPR pressure alone exceeds the
- // number of addressable registers in each category.
- const unsigned MaxArchVGPRs = ST.getAddressableNumArchVGPRs();
- if (NumArchVGPRs > MaxArchVGPRs) {
- ArchVGPRs = NumArchVGPRs - MaxArchVGPRs;
- NumArchVGPRs = MaxArchVGPRs;
- }
- if (NumAGPRs > MaxArchVGPRs) {
- AGPRs = NumAGPRs - MaxArchVGPRs;
- NumAGPRs = MaxArchVGPRs;
- }
-
- // Check overall VGPR usage against the limit; any excess above addressable
- // register limits has already been accounted for.
- const unsigned Granule = AMDGPU::IsaInfo::getArchVGPRAllocGranule();
- unsigned NumVGPRs = GCNRegPressure::getUnifiedVGPRNum(NumArchVGPRs, NumAGPRs);
- if (NumVGPRs > MaxVGPRs) {
- VGPRs = NumVGPRs - MaxVGPRs;
- ArchVGPRsToAlignment = NumArchVGPRs - alignDown(NumArchVGPRs, Granule);
- if (!ArchVGPRsToAlignment)
- ArchVGPRsToAlignment = Granule;
- }
-}
-
-bool ExcessRP::saveArchVGPRs(unsigned NumRegs) {
- bool Progress = saveRegs(ArchVGPRs, NumRegs);
- if (!NumRegs)
- return Progress;
-
- if (!UnifiedRF) {
- if (CombineVGPRSavings)
- Progress |= saveRegs(AGPRs, NumRegs);
- } else if (HasAGPRs && (VGPRs || (CombineVGPRSavings && AGPRs))) {
- // There is progress as long as there are VGPRs left to save, even if the
- // save induced by this particular call does not cross an ArchVGPR alignment
- // barrier.
- Progress = true;
-
- // ArchVGPRs can only be allocated as a multiple of a granule in unified RF.
- unsigned NumSavedRegs = 0;
-
- // Count the number of whole ArchVGPR allocation granules we can save.
- const unsigned Granule = AMDGPU::IsaInfo::getArchVGPRAllocGranule();
- if (unsigned NumGranules = NumRegs / Granule; NumGranules) {
- NumSavedRegs = NumGranules * Granule;
- NumRegs -= NumSavedRegs;
- }
-
- // We may be able to save one more whole ArchVGPR allocation granule.
- if (NumRegs >= ArchVGPRsToAlignment) {
- NumSavedRegs += Granule;
- ArchVGPRsToAlignment = Granule - (NumRegs - ArchVGPRsToAlignment);
- } else {
- ArchVGPRsToAlignment -= NumRegs;
- }
-
- // Prioritize saving generic VGPRs, then AGPRs if we consider that the
- // register allocator will be able to replace an AGPR with an ArchVGPR.
- saveRegs(VGPRs, NumSavedRegs);
- if (CombineVGPRSavings)
- saveRegs(AGPRs, NumSavedRegs);
- } else {
- // No AGPR usage in the region i.e., no allocation granule to worry about.
- Progress |= saveRegs(VGPRs, NumRegs);
- }
- return Progress;
-}
-
-bool ExcessRP::saveAGPRs(unsigned NumRegs) {
- bool Progress = saveRegs(AGPRs, NumRegs);
- if (UnifiedRF)
- Progress |= saveRegs(VGPRs, NumRegs);
- if (CombineVGPRSavings)
- Progress |= saveRegs(ArchVGPRs, NumRegs);
- return Progress;
-}
-
bool PreRARematStage::canIncreaseOccupancyOrReduceSpill() {
- const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo *>(DAG.TRI);
-
REMAT_DEBUG({
dbgs() << "Collecting rematerializable instructions in ";
MF.getFunction().printAsOperand(dbgs(), false);
dbgs() << '\n';
});
- // Maps optimizable regions (i.e., regions at minimum and VGPR-limited
- // occupancy, or regions with VGPR spilling) to a model of their excess RP.
- DenseMap<unsigned, ExcessRP> OptRegions;
+ // Maps optimizable regions (i.e., regions at minimum and register-limited
+ // occupancy, or regions with spilling) to the target RP we would like to
+ // reach.
+ DenseMap<unsigned, GCNRPTarget> OptRegions;
const Function &F = MF.getFunction();
unsigned DynamicVGPRBlockSize =
MF.getInfo<SIMachineFunctionInfo>()->getDynamicVGPRBlockSize();
@@ -1901,32 +1734,35 @@ bool PreRARematStage::canIncreaseOccupancyOrReduceSpill() {
// the register allocator i.e., the scheduler will not be able to reason
// about these savings and will not report an increase in the achievable
// occupancy, triggering rollbacks.
- ExcessRP Excess(ST, RP, MaxSGPRsNoSpill, MaxVGPRsNoSpill,
- /*CombineVGPRSavings=*/true);
- if (Excess && IncreaseOccupancy) {
+ GCNRPTarget Target(MaxSGPRsNoSpill, MaxVGPRsNoSpill, MF, RP,
+ /*CombineVGPRSavings=*/true);
+ if (!Target.satisfied() && IncreaseOccupancy) {
// There is spilling in the region and we were so far trying to increase
// occupancy. Strop trying that and focus on reducing spilling.
IncreaseOccupancy = false;
OptRegions.clear();
} else if (IncreaseOccupancy) {
// There is no spilling in the region, try to increase occupancy.
- Excess = ExcessRP(ST, RP, MaxSGPRsIncOcc, MaxVGPRsIncOcc,
- /*CombineVGPRSavings=*/false);
+ Target = GCNRPTarget(MaxSGPRsIncOcc, MaxVGPRsIncOcc, MF, RP,
+ /*CombineVGPRSavings=*/false);
}
- if (Excess)
- OptRegions.insert({I, Excess});
+ if (!Target.satisfied())
+ OptRegions.insert({I, Target});
}
if (OptRegions.empty())
return false;
#ifndef NDEBUG
- if (IncreaseOccupancy)
- REMAT_DEBUG(dbgs() << "Occupancy minimal in regions:\n");
- else
- REMAT_DEBUG(dbgs() << "Spilling in regions:\n");
+ if (IncreaseOccupancy) {
+ REMAT_DEBUG(dbgs() << "Occupancy minimal (" << DAG.MinOccupancy
+ << ") in regions:\n");
+ } else {
+ REMAT_DEBUG(dbgs() << "Spilling w.r.t. minimum target occupancy ("
+ << WavesPerEU.first << ") in regions:\n");
+ }
for (unsigned I = 0, E = DAG.Regions.size(); I != E; ++I) {
if (auto OptIt = OptRegions.find(I); OptIt != OptRegions.end())
- REMAT_DEBUG(dbgs() << " " << I << ": " << OptIt->getSecond() << '\n');
+ REMAT_DEBUG(dbgs() << " [" << I << "] " << OptIt->getSecond() << '\n');
}
#endif
@@ -1941,18 +1777,14 @@ bool PreRARematStage::canIncreaseOccupancyOrReduceSpill() {
// estimate that we have identified enough rematerialization opportunities to
// achieve our goal, and sets Progress to true when this particular reduction
// in pressure was helpful toward that goal.
- auto ReduceRPInRegion = [&](auto OptIt, LaneBitmask Mask,
- ...
[truncated]
|
arsenm
approved these changes
Jun 26, 2025
| if (OptRegions.empty()) | ||
| return false; | ||
|
|
||
| #ifndef NDEBUG |
Contributor
There was a problem hiding this comment.
Might as well move this whole thing into a REMAT_DEBUG({}) instead of doing it on each statement
Contributor
Author
There was a problem hiding this comment.
Sounds good, will do this in my upcoming change to the stage which will touch this part of the code anyway.
Collaborator
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/162/builds/25392 Here is the relevant piece of the build log for the reference |
anthonyhatran
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to anthonyhatran/llvm-project
that referenced
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Jun 26, 2025
llvm#145765) This adds the `GCNRPTarget` class which models a register pressure target (i.e., maximum number of SGPRs/VGPRS) that one can track register savings against. The only current use of this class is in the scheduler's rematerialization stage. It replaces the more ad-hoc (and now deleted) `ExcessRP` class which used to serve the same purpose. This is only NFC~ish because `GCNRPTarget` tracks VGPR usage more accurately than `ExcessRP` used to. To estimate required combined VGPR savings we now additionally take into account the number of available VGPRs in both banks (ArchVGPR and AGPR) at the time where the RP target is created, whereas we used to only consider explicit savings made from the starting RP. This makes VGPR savings estimations more accurate in cases where we allow for savings in one VGPR bank to help towards reducing pressure in another VGPR bank (see `GCNRPTarget::CombineVGPRSavings`). This is the cause for unit test changes.
jrbyrnes
pushed a commit
to jrbyrnes/llvm-project
that referenced
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Aug 13, 2025
llvm#145765) This adds the `GCNRPTarget` class which models a register pressure target (i.e., maximum number of SGPRs/VGPRS) that one can track register savings against. The only current use of this class is in the scheduler's rematerialization stage. It replaces the more ad-hoc (and now deleted) `ExcessRP` class which used to serve the same purpose. This is only NFC~ish because `GCNRPTarget` tracks VGPR usage more accurately than `ExcessRP` used to. To estimate required combined VGPR savings we now additionally take into account the number of available VGPRs in both banks (ArchVGPR and AGPR) at the time where the RP target is created, whereas we used to only consider explicit savings made from the starting RP. This makes VGPR savings estimations more accurate in cases where we allow for savings in one VGPR bank to help towards reducing pressure in another VGPR bank (see `GCNRPTarget::CombineVGPRSavings`). This is the cause for unit test changes.
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This adds the
GCNRPTargetclass which models a register pressure target (i.e., maximum number of SGPRs/VGPRS) that one can track register savings against. The only current use of this class is in the scheduler's rematerialization stage. It replaces the more ad-hoc (and now deleted)ExcessRPclass which used to serve the same purpose.This is only NFC~ish because
GCNRPTargettracks VGPR usage more accurately thanExcessRPused to. To estimate required combined VGPR savings we now additionally take into account the number of available VGPRs in both banks (ArchVGPR and AGPR) at the time where the RP target is created, whereas we used to only consider explicit savings made from the starting RP. This makes VGPR savings estimations more accurate in cases where we allow for savings in one VGPR bank to help towards reducing pressure in another VGPR bank (seeGCNRPTarget::CombineVGPRSavings). This is the cause for unit test changes.