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[Hexagon] NFC: Reduce the amount of version-specific code #145812

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Merged
merged 1 commit into from
Jun 27, 2025
Merged

[Hexagon] NFC: Reduce the amount of version-specific code #145812

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41 changes: 15 additions & 26 deletions clang/lib/Basic/Targets/Hexagon.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,19 @@
using namespace clang;
using namespace clang::targets;

namespace {

constexpr llvm::StringLiteral CpuValsTextArray[] = {
"hexagonv5", "hexagonv55", "hexagonv60", "hexagonv62", "hexagonv65",
"hexagonv66", "hexagonv67", "hexagonv67t", "hexagonv68", "hexagonv69",
"hexagonv71", "hexagonv71t", "hexagonv73", "hexagonv75", "hexagonv79",
};

} // namespace

const llvm::ArrayRef<llvm::StringLiteral>
HexagonTargetInfo::CpuValsText(CpuValsTextArray);

void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__qdsp6__", "1");
Expand Down Expand Up @@ -239,22 +252,6 @@ bool HexagonTargetInfo::hasFeature(StringRef Feature) const {
.Default(false);
}

struct CPUSuffix {
llvm::StringLiteral Name;
llvm::StringLiteral Suffix;
};

static constexpr CPUSuffix Suffixes[] = {
{{"hexagonv5"}, {"5"}}, {{"hexagonv55"}, {"55"}},
{{"hexagonv60"}, {"60"}}, {{"hexagonv62"}, {"62"}},
{{"hexagonv65"}, {"65"}}, {{"hexagonv66"}, {"66"}},
{{"hexagonv67"}, {"67"}}, {{"hexagonv67t"}, {"67t"}},
{{"hexagonv68"}, {"68"}}, {{"hexagonv69"}, {"69"}},
{{"hexagonv71"}, {"71"}}, {{"hexagonv71t"}, {"71t"}},
{{"hexagonv73"}, {"73"}}, {{"hexagonv75"}, {"75"}},
{{"hexagonv79"}, {"79"}},
};

std::optional<unsigned> HexagonTargetInfo::getHexagonCPURev(StringRef Name) {
StringRef Arch = Name;
Arch.consume_front("hexagonv");
Expand All @@ -267,18 +264,10 @@ std::optional<unsigned> HexagonTargetInfo::getHexagonCPURev(StringRef Name) {
return std::nullopt;
}

const char *HexagonTargetInfo::getHexagonCPUSuffix(StringRef Name) {
const CPUSuffix *Item = llvm::find_if(
Suffixes, [Name](const CPUSuffix &S) { return S.Name == Name; });
if (Item == std::end(Suffixes))
return nullptr;
return Item->Suffix.data();
}

void HexagonTargetInfo::fillValidCPUList(
SmallVectorImpl<StringRef> &Values) const {
for (const CPUSuffix &Suffix : Suffixes)
Values.push_back(Suffix.Name);
for (const llvm::StringLiteral &I : CpuValsText)
Values.push_back(I);
}

llvm::SmallVector<Builtin::InfosShard>
Expand Down
5 changes: 3 additions & 2 deletions clang/lib/Basic/Targets/Hexagon.h
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Expand Up @@ -25,6 +25,7 @@ namespace targets {
// Hexagon abstract base class
class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo {

static const llvm::ArrayRef<llvm::StringLiteral> CpuValsText;
static const char *const GCCRegNames[];
static const TargetInfo::GCCRegAlias GCCRegAliases[];
std::string CPU;
Expand Down Expand Up @@ -115,11 +116,11 @@ class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo {

std::string_view getClobbers() const override { return ""; }

static const char *getHexagonCPUSuffix(StringRef Name);
static std::optional<unsigned> getHexagonCPURev(StringRef Name);

bool isValidCPUName(StringRef Name) const override {
return getHexagonCPUSuffix(Name);
return std::any_of(std::begin(CpuValsText), std::end(CpuValsText),
[Name](StringRef V) { return V == Name; });
}

void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
Expand Down
20 changes: 0 additions & 20 deletions llvm/lib/Target/Hexagon/HexagonDepArch.h
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Expand Up @@ -32,26 +32,6 @@ enum class ArchEnum {
V79
};

inline std::optional<Hexagon::ArchEnum> getCpu(StringRef CPU) {
return StringSwitch<std::optional<Hexagon::ArchEnum>>(CPU)
.Case("generic", Hexagon::ArchEnum::V5)
.Case("hexagonv5", Hexagon::ArchEnum::V5)
.Case("hexagonv55", Hexagon::ArchEnum::V55)
.Case("hexagonv60", Hexagon::ArchEnum::V60)
.Case("hexagonv62", Hexagon::ArchEnum::V62)
.Case("hexagonv65", Hexagon::ArchEnum::V65)
.Case("hexagonv66", Hexagon::ArchEnum::V66)
.Case("hexagonv67", Hexagon::ArchEnum::V67)
.Case("hexagonv67t", Hexagon::ArchEnum::V67)
.Case("hexagonv68", Hexagon::ArchEnum::V68)
.Case("hexagonv69", Hexagon::ArchEnum::V69)
.Case("hexagonv71", Hexagon::ArchEnum::V71)
.Case("hexagonv71t", Hexagon::ArchEnum::V71)
.Case("hexagonv73", Hexagon::ArchEnum::V73)
.Case("hexagonv75", Hexagon::ArchEnum::V75)
.Case("hexagonv79", Hexagon::ArchEnum::V79)
.Default(std::nullopt);
}
} // namespace Hexagon
} // namespace llvm

Expand Down
8 changes: 1 addition & 7 deletions llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
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Expand Up @@ -88,12 +88,6 @@ HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,

HexagonSubtarget &
HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
std::optional<Hexagon::ArchEnum> ArchVer = Hexagon::getCpu(CPUString);
if (ArchVer)
HexagonArchVersion = *ArchVer;
else
llvm_unreachable("Unrecognized Hexagon processor version");

UseHVX128BOps = false;
UseHVX64BOps = false;
UseAudioOps = false;
Expand Down Expand Up @@ -163,7 +157,7 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
FeatureBitset FeatureBits = getFeatureBits();
if (HexagonDisableDuplex)
setFeatureBits(FeatureBits.reset(Hexagon::FeatureDuplex));
setFeatureBits(Hexagon_MC::completeHVXFeatures(FeatureBits));
SetFeatureBitsTransitively(Hexagon_MC::completeHVXFeatures(FeatureBits));

return *this;
}
Expand Down
51 changes: 4 additions & 47 deletions llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
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Expand Up @@ -149,57 +149,14 @@ void HexagonMCELFStreamer::HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol,
HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment, AccessSize);
}

static unsigned featureToArchVersion(unsigned Feature) {
switch (Feature) {
case Hexagon::ArchV5:
return 5;
case Hexagon::ArchV55:
return 55;
case Hexagon::ArchV60:
case Hexagon::ExtensionHVXV60:
return 60;
case Hexagon::ArchV62:
case Hexagon::ExtensionHVXV62:
return 62;
case Hexagon::ArchV65:
case Hexagon::ExtensionHVXV65:
return 65;
case Hexagon::ArchV66:
case Hexagon::ExtensionHVXV66:
return 66;
case Hexagon::ArchV67:
case Hexagon::ExtensionHVXV67:
return 67;
case Hexagon::ArchV68:
case Hexagon::ExtensionHVXV68:
return 68;
case Hexagon::ArchV69:
case Hexagon::ExtensionHVXV69:
return 69;
case Hexagon::ArchV71:
case Hexagon::ExtensionHVXV71:
return 71;
case Hexagon::ArchV73:
case Hexagon::ExtensionHVXV73:
return 73;
case Hexagon::ArchV75:
case Hexagon::ExtensionHVXV75:
return 75;
case Hexagon::ArchV79:
case Hexagon::ExtensionHVXV79:
return 79;
}
llvm_unreachable("Expected valid arch feature");
return 0;
}

void HexagonTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
auto Features = STI.getFeatureBits();
unsigned Arch = featureToArchVersion(Hexagon_MC::getArchVersion(Features));
std::optional<unsigned> HVXArch = Hexagon_MC::getHVXVersion(Features);
unsigned Arch = Hexagon_MC::getArchVersionAttribute(Features).value_or(0);
std::optional<unsigned> HVXArch =
Hexagon_MC::getHVXVersionAttribute(Features);
emitAttribute(HexagonAttrs::ARCH, Arch);
if (HVXArch)
emitAttribute(HexagonAttrs::HVXARCH, featureToArchVersion(*HVXArch));
emitAttribute(HexagonAttrs::HVXARCH, *HVXArch);
if (Features.test(Hexagon::ExtensionHVXIEEEFP))
emitAttribute(HexagonAttrs::HVXIEEEFP, 1);
if (Features.test(Hexagon::ExtensionHVXQFloat))
Expand Down
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