Skip to content

[X86] lowerShuffleAsVTRUNC - use combineConcatVectorOps to catch more "cheap" concats #145876

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jun 26, 2025
Merged

[X86] lowerShuffleAsVTRUNC - use combineConcatVectorOps to catch more "cheap" concats #145876

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
42 changes: 16 additions & 26 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10312,6 +10312,11 @@ static bool isNonZeroElementsInOrder(const APInt &Zeroable,
return true;
}

static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
ArrayRef<SDValue> Ops, SelectionDAG &DAG,
const X86Subtarget &Subtarget,
unsigned Depth = 0);

/// Try to lower a shuffle with a single PSHUFB of V1 or V2.
static SDValue lowerShuffleWithPSHUFB(const SDLoc &DL, MVT VT,
ArrayRef<int> Mask, SDValue V1,
Expand Down Expand Up @@ -10692,7 +10697,8 @@ static SDValue lowerShuffleAsVTRUNC(const SDLoc &DL, MVT VT, SDValue V1,
SelectionDAG &DAG) {
assert((VT.is128BitVector() || VT.is256BitVector()) &&
"Unexpected VTRUNC type");
if (!Subtarget.hasAVX512())
if (!Subtarget.hasAVX512() ||
(VT.is256BitVector() && !Subtarget.useAVX512Regs()))
return SDValue();

unsigned NumElts = VT.getVectorNumElements();
Expand Down Expand Up @@ -10721,30 +10727,19 @@ static SDValue lowerShuffleAsVTRUNC(const SDLoc &DL, MVT VT, SDValue V1,
bool UndefUppers =
UpperElts > 0 && isUndefInRange(Mask, NumSrcElts, UpperElts);

// As we're using both sources then we need to concat them together
// and truncate from the double-sized src.
MVT ConcatVT = VT.getDoubleNumVectorElementsVT();

// For offset truncations, ensure that the concat is cheap.
if (Offset) {
auto IsCheapConcat = [&](SDValue Lo, SDValue Hi) {
if (Lo.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
Hi.getOpcode() == ISD::EXTRACT_SUBVECTOR)
return Lo.getOperand(0) == Hi.getOperand(0);
if (ISD::isNormalLoad(Lo.getNode()) &&
ISD::isNormalLoad(Hi.getNode())) {
auto *LDLo = cast<LoadSDNode>(Lo);
auto *LDHi = cast<LoadSDNode>(Hi);
return DAG.areNonVolatileConsecutiveLoads(
LDHi, LDLo, Lo.getValueType().getStoreSize(), 1);
}
return false;
};
if (!IsCheapConcat(peekThroughBitcasts(V1), peekThroughBitcasts(V2)))
SDValue Src =
combineConcatVectorOps(DL, ConcatVT, {V1, V2}, DAG, Subtarget);
if (!Src) {
if (Offset)
continue;
Src = DAG.getNode(ISD::CONCAT_VECTORS, DL, ConcatVT, V1, V2);
}

// As we're using both sources then we need to concat them together
// and truncate from the double-sized src.
MVT ConcatVT = MVT::getVectorVT(VT.getScalarType(), NumElts * 2);
SDValue Src = DAG.getNode(ISD::CONCAT_VECTORS, DL, ConcatVT, V1, V2);

MVT SrcSVT = MVT::getIntegerVT(SrcEltBits);
MVT SrcVT = MVT::getVectorVT(SrcSVT, NumSrcElts);
Src = DAG.getBitcast(SrcVT, Src);
Expand Down Expand Up @@ -42183,11 +42178,6 @@ static SDValue canonicalizeLaneShuffleWithRepeatedOps(SDValue V,
return SDValue();
}

static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
ArrayRef<SDValue> Ops, SelectionDAG &DAG,
const X86Subtarget &Subtarget,
unsigned Depth = 0);

/// Try to combine x86 target specific shuffles.
static SDValue combineTargetShuffle(SDValue N, const SDLoc &DL,
SelectionDAG &DAG,
Expand Down
Loading