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[CostModel/RISCV] Fix costs of vector [l](lrint|lround) #146058

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Merged
merged 3 commits into from
Jul 29, 2025
Merged

[CostModel/RISCV] Fix costs of vector [l](lrint|lround) #146058

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[CostModel/RISCV] Fix costs of [l]lrint
artagnon Jun 27, 2025
580b90d
[CostModel] Address review
artagnon Jul 29, 2025
d1acd1d
[CostModel] Address another review
artagnon Jul 29, 2025
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45 changes: 37 additions & 8 deletions llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1191,9 +1191,6 @@ static const CostTblEntry VectorIntrinsicCostTable[]{
{Intrinsic::roundeven, MVT::f64, 9},
{Intrinsic::rint, MVT::f32, 7},
{Intrinsic::rint, MVT::f64, 7},
{Intrinsic::lrint, MVT::i32, 1},
{Intrinsic::lrint, MVT::i64, 1},
{Intrinsic::llrint, MVT::i64, 1},
{Intrinsic::nearbyint, MVT::f32, 9},
{Intrinsic::nearbyint, MVT::f64, 9},
{Intrinsic::bswap, MVT::i16, 3},
Expand Down Expand Up @@ -1251,11 +1248,43 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
switch (ICA.getID()) {
case Intrinsic::lrint:
case Intrinsic::llrint:
// We can't currently lower half or bfloat vector lrint/llrint.
if (auto *VecTy = dyn_cast<VectorType>(ICA.getArgTypes()[0]);
VecTy && VecTy->getElementType()->is16bitFPTy())
return InstructionCost::getInvalid();
[[fallthrough]];
case Intrinsic::lround:
case Intrinsic::llround: {
auto LT = getTypeLegalizationCost(RetTy);
Type *SrcTy = ICA.getArgTypes().front();
auto SrcLT = getTypeLegalizationCost(SrcTy);
if (ST->hasVInstructions() && LT.second.isVector()) {
ArrayRef<unsigned> Ops;
unsigned SrcEltSz = DL.getTypeSizeInBits(SrcTy->getScalarType());
unsigned DstEltSz = DL.getTypeSizeInBits(RetTy->getScalarType());
if (LT.second.getVectorElementType() == MVT::bf16) {
if (!ST->hasVInstructionsBF16Minimal())
return InstructionCost::getInvalid();
if (DstEltSz == 32)
Ops = {RISCV::VFWCVTBF16_F_F_V, RISCV::VFCVT_X_F_V};
else
Ops = {RISCV::VFWCVTBF16_F_F_V, RISCV::VFWCVT_X_F_V};
} else if (LT.second.getVectorElementType() == MVT::f16 &&
!ST->hasVInstructionsF16()) {
if (!ST->hasVInstructionsF16Minimal())
return InstructionCost::getInvalid();
if (DstEltSz == 32)
Ops = {RISCV::VFWCVT_F_F_V, RISCV::VFCVT_X_F_V};
else
Ops = {RISCV::VFWCVT_F_F_V, RISCV::VFWCVT_X_F_V};

} else if (SrcEltSz > DstEltSz) {
Ops = {RISCV::VFNCVT_X_F_W};
} else if (SrcEltSz < DstEltSz) {
Ops = {RISCV::VFWCVT_X_F_V};
} else {
Ops = {RISCV::VFCVT_X_F_V};
}
return std::max(SrcLT.first, LT.first) *
getRISCVInstructionCost(Ops, LT.second, CostKind);
}
break;
}
case Intrinsic::ceil:
case Intrinsic::floor:
case Intrinsic::trunc:
Expand Down
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