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[ISel/RISCV] Improve code in lowerFCOPYSIGN (NFC) #146061

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Merged
merged 1 commit into from
Jun 27, 2025
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[ISel/RISCV] Improve code in lowerFCOPYSIGN (NFC) #146061

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46 changes: 23 additions & 23 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6848,32 +6848,32 @@ static SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG,
SDLoc DL(Op);

// Get sign bit into an integer value.
SDValue SignAsInt;
unsigned SignSize = Sign.getValueSizeInBits();
if (SignSize == Subtarget.getXLen()) {
SignAsInt = DAG.getNode(ISD::BITCAST, DL, XLenVT, Sign);
} else if (SignSize == 16) {
SignAsInt = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, XLenVT, Sign);
} else if (SignSize == 32) {
SignAsInt = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, XLenVT, Sign);
} else if (SignSize == 64) {
assert(XLenVT == MVT::i32 && "Unexpected type");
// Copy the upper word to integer.
SignAsInt = DAG.getNode(RISCVISD::SplitF64, DL, {MVT::i32, MVT::i32}, Sign)
.getValue(1);
SignSize = 32;
} else
llvm_unreachable("Unexpected sign size");
SDValue SignAsInt = [&]() {
if (SignSize == Subtarget.getXLen())
return DAG.getNode(ISD::BITCAST, DL, XLenVT, Sign);
switch (SignSize) {
case 16:
return DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, XLenVT, Sign);
case 32:
return DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, XLenVT, Sign);
case 64: {
assert(XLenVT == MVT::i32 && "Unexpected type");
// Copy the upper word to integer.
SignSize = 32;
return DAG.getNode(RISCVISD::SplitF64, DL, {MVT::i32, MVT::i32}, Sign)
.getValue(1);
}
default:
llvm_unreachable("Unexpected sign size");
}
}();

// Get the signbit at the right position for MagAsInt.
int ShiftAmount = (int)SignSize - (int)Mag.getValueSizeInBits();
if (ShiftAmount > 0) {
SignAsInt = DAG.getNode(ISD::SRL, DL, XLenVT, SignAsInt,
DAG.getConstant(ShiftAmount, DL, XLenVT));
} else if (ShiftAmount < 0) {
SignAsInt = DAG.getNode(ISD::SHL, DL, XLenVT, SignAsInt,
DAG.getConstant(-ShiftAmount, DL, XLenVT));
}
if (int ShiftAmount = (int)SignSize - (int)Mag.getValueSizeInBits())
SignAsInt = DAG.getNode(ShiftAmount > 0 ? ISD::SRL : ISD::SHL, DL, XLenVT,
SignAsInt,
DAG.getConstant(std::abs(ShiftAmount), DL, XLenVT));

// Mask the sign bit and any bits above it. The extra bits will be dropped
// when we convert back to FP.
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