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[ISel] Commute FMUL and inserting zero into vector lane #146096

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[ISel] Commute FMUL and inserting zero into vector lane #146096

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93a6be0
Add test for inserting zero into vector lane of fmul result
juliannagele Jun 27, 2025
e08422d
[ISel] Commute FMUL and inserting zero into vector lane
juliannagele Jun 27, 2025
e3b38a9
fixup! [ISel] Commute FMUL and inserting zero into vector lane
juliannagele Jul 11, 2025
24c4f36
Merge branch 'main' into commute-insertzero-fmul
juliannagele Jul 17, 2025
9cd5327
fixup! fixup! [ISel] Commute FMUL and inserting zero into vector lane
juliannagele Jul 17, 2025
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32 changes: 32 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -26268,11 +26268,43 @@ static SDValue removeRedundantInsertVectorElt(SDNode *N) {
return ExtractVec;
}

static SDValue commuteInsertVectorEltFMul(SDNode *N, SelectionDAG &DAG) {
assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT && "Unexpected node!");
SDValue InsertVec = N->getOperand(0);
SDValue InsertVal = N->getOperand(1);
SDValue InsertIdx = N->getOperand(2);

// Only handle constant 0 insertion...
if (!(isNullConstant(InsertVal) || isNullFPConstant(InsertVal)))
return SDValue();
// ... into the result of an FMUL.
if (InsertVec.getOpcode() != ISD::FMUL)
return SDValue();

// Insert into the operand of FMUL instead.
SDValue FMulOp = InsertVec.getOperand(0);

if (!InsertVec.hasOneUse() || !FMulOp.hasOneUse())
return SDValue();

SDValue InsertOp =
DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), FMulOp.getValueType(),
FMulOp, InsertVal, InsertIdx);
SDValue FMul =
DAG.getNode(ISD::FMUL, SDLoc(InsertVec), InsertVec.getValueType(),
InsertOp, InsertVec.getOperand(1));
DAG.ReplaceAllUsesWith(N, &FMul);
return FMul;
}

static SDValue
performInsertVectorEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
if (SDValue Res = removeRedundantInsertVectorElt(N))
return Res;

if (SDValue Res = commuteInsertVectorEltFMul(N, DCI.DAG))
return Res;

return performPostLD1Combine(N, DCI, true);
}

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10 changes: 10 additions & 0 deletions llvm/test/CodeGen/AArch64/arm64-vmul.ll
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Expand Up @@ -1186,6 +1186,16 @@ define double @fmul_lane_d(double %A, <2 x double> %vec) nounwind {
ret double %res
}

define <4 x float> @fmul_insert_zero(<4 x float> %A, <4 x float> %B) {
; CHECK-LABEL: fmul_insert_zero:
; CHECK: // %bb.0:
; CHECK-NEXT: mov.s v0[3], wzr
; CHECK-NEXT: fmul.4s v0, v0, v1
; CHECK-NEXT: ret
%mul = fmul <4 x float> %A, %B
%mul_set_lane = insertelement <4 x float> %mul, float 0.000000e+00, i64 3
ret <4 x float> %mul_set_lane
}


define <2 x float> @fmulx_lane_2s(<2 x float> %A, <2 x float> %B) nounwind {
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