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Merged
merged 1 commit into from
Aug 13, 2025
Merged

[AArch64][llvm] Unify AArch64 tests into a single file (3/4) (NFC) #146330

merged 1 commit into from
Aug 13, 2025

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@jthackray
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@jthackray jthackray commented Jun 30, 2025 •
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This is a series of patches (3/4) to unify assembly/disassembly of recent AArch64 tests into a single file. The aim is to improve consistency, so that all instructions and system registers are thoroughly tested, and future test cases will be in a unified format.

This patch:

  • removes .txt tests which have multiple feature dependencies
  • makes the .s tests have a roundabout run line to test both encoding and assembly
  • creates diagnostic tests when needed

See also #146328, #146329 and #146331.

@llvmbot llvmbot added backend:AArch64 llvm:mc Machine (object) code labels Jun 30, 2025
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llvmbot commented Jun 30, 2025

@llvm/pr-subscribers-backend-aarch64

Author: Jonathan Thackray (jthackray)

Changes

This is a series of patches (3/4) to unify assembly/disassembly of recent AArch64 tests into a single file. The aim is to improve consistency, so that all instructions and system registers are thoroughly tested, and future test cases will be in a unified format.

This patch:

  • removes .txt tests which have multiple feature dependancies
  • makes the .s tests have a roundabout run line to test both encoding and assembly
  • creates diagnostic tests when needed

Patch is 461.48 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/146330.diff

29 Files Affected:

  • (modified) llvm/test/MC/AArch64/armv8.6a-fgt.s (+105-47)
  • (added) llvm/test/MC/AArch64/armv8.8a-mops-diagnostics.s (+227)
  • (modified) llvm/test/MC/AArch64/armv8.8a-mops.s (+569-488)
  • (modified) llvm/test/MC/AArch64/armv8.9a-clrbhb.s (+29-16)
  • (modified) llvm/test/MC/AArch64/armv8.9a-debug-pmu.s (+1560-467)
  • (modified) llvm/test/MC/AArch64/armv8.9a-lrcpc3.s (+237-138)
  • (modified) llvm/test/MC/AArch64/armv8.9a-specres2.s (+27-8)
  • (added) llvm/test/MC/AArch64/armv8.9a-the-diagnostics.s (+103)
  • (modified) llvm/test/MC/AArch64/armv8.9a-the.s (+677-572)
  • (added) llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s (+30)
  • (modified) llvm/test/MC/AArch64/armv9-mrrs.s (+235-92)
  • (added) llvm/test/MC/AArch64/armv9-msrr-diagnostics.s (+30)
  • (modified) llvm/test/MC/AArch64/armv9-msrr.s (+125-95)
  • (added) llvm/test/MC/AArch64/armv9-sysp-diagnostics.s (+35)
  • (removed) llvm/test/MC/AArch64/armv9-sysp.s (-538)
  • (modified) llvm/test/MC/AArch64/armv9.4a-chk.s (+26-9)
  • (modified) llvm/test/MC/AArch64/armv9.5a-tlbiw.s (+38-15)
  • (added) llvm/test/MC/AArch64/armv9a-sysp.s (+834)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt (-75)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv8.8a-mops.txt (-434)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv8.9a-clrbhb.txt (-16)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv8.9a-debug-pmu.txt (-730)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt (-113)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv8.9a-specres2.txt (-16)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv8.9a-the.txt (-482)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv9-sysp.txt (-562)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv9-sysreg128.txt (-147)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv9.4a-chk.txt (-8)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv9.5a-tlbiw.txt (-27)
diff --git a/llvm/test/MC/AArch64/armv8.6a-fgt.s b/llvm/test/MC/AArch64/armv8.6a-fgt.s
index 11002aca5e1a0..4b825ea191a68 100644
--- a/llvm/test/MC/AArch64/armv8.6a-fgt.s
+++ b/llvm/test/MC/AArch64/armv8.6a-fgt.s
@@ -1,75 +1,133 @@
-// RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+fgt   < %s | FileCheck %s
-// RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+v8.6a < %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64 -show-encoding  < %s 2>&1         | FileCheck %s --check-prefix=NOFGT
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v8.6a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fgt < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fgt < %s \
+// RUN:        | llvm-objdump -d --mattr=+fgt - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fgt < %s \
+// RUN:   | llvm-objdump -d --mattr=-fgt - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fgt < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+fgt -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
 
 msr HFGRTR_EL2, x0
+// CHECK-INST: msr HFGRTR_EL2, x0
+// CHECK-ENCODING: encoding: [0x80,0x11,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c1180      msr S3_4_C1_C1_4, x0
 msr HFGWTR_EL2, x5
+// CHECK-INST: msr HFGWTR_EL2, x5
+// CHECK-ENCODING: encoding: [0xa5,0x11,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c11a5      msr S3_4_C1_C1_5, x5
 msr HFGITR_EL2, x10
+// CHECK-INST: msr HFGITR_EL2, x10
+// CHECK-ENCODING: encoding: [0xca,0x11,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c11ca      msr S3_4_C1_C1_6, x10
 msr HDFGRTR_EL2, x15
+// CHECK-INST: msr HDFGRTR_EL2, x15
+// CHECK-ENCODING: encoding: [0x8f,0x31,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c318f      msr S3_4_C3_C1_4, x15
 msr HDFGWTR_EL2, x20
+// CHECK-INST: msr HDFGWTR_EL2, x20
+// CHECK-ENCODING: encoding: [0xb4,0x31,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c31b4      msr S3_4_C3_C1_5, x20
 msr HAFGRTR_EL2, x25
-// CHECK: msr     HFGRTR_EL2, x0          // encoding: [0x80,0x11,0x1c,0xd5]
-// CHECK: msr     HFGWTR_EL2, x5          // encoding: [0xa5,0x11,0x1c,0xd5]
-// CHECK: msr     HFGITR_EL2, x10         // encoding: [0xca,0x11,0x1c,0xd5]
-// CHECK: msr     HDFGRTR_EL2, x15        // encoding: [0x8f,0x31,0x1c,0xd5]
-// CHECK: msr     HDFGWTR_EL2, x20        // encoding: [0xb4,0x31,0x1c,0xd5]
-// CHECK: msr     HAFGRTR_EL2, x25        // encoding: [0xd9,0x31,0x1c,0xd5]
-// NOFGT: error: expected writable system register or pstate
-// NOFGT: error: expected writable system register or pstate
-// NOFGT: error: expected writable system register or pstate
-// NOFGT: error: expected writable system register or pstate
-// NOFGT: error: expected writable system register or pstate
-// NOFGT: error: expected writable system register or pstate
+// CHECK-INST: msr HAFGRTR_EL2, x25
+// CHECK-ENCODING: encoding: [0xd9,0x31,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c31d9      msr S3_4_C3_C1_6, x25
 
 mrs x30,  HFGRTR_EL2
+// CHECK-INST: mrs x30, HFGRTR_EL2
+// CHECK-ENCODING: encoding: [0x9e,0x11,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register
+// CHECK-UNKNOWN:  d53c119e      mrs x30, S3_4_C1_C1_4
 mrs x25,  HFGWTR_EL2
+// CHECK-INST: mrs x25, HFGWTR_EL2
+// CHECK-ENCODING: encoding: [0xb9,0x11,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register
+// CHECK-UNKNOWN:  d53c11b9      mrs x25, S3_4_C1_C1_5
 mrs x20,  HFGITR_EL2
+// CHECK-INST: mrs x20, HFGITR_EL2
+// CHECK-ENCODING: encoding: [0xd4,0x11,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register
+// CHECK-UNKNOWN:  d53c11d4      mrs x20, S3_4_C1_C1_6
 mrs x15,  HDFGRTR_EL2
+// CHECK-INST: mrs x15, HDFGRTR_EL2
+// CHECK-ENCODING: encoding: [0x8f,0x31,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register
+// CHECK-UNKNOWN:  d53c318f      mrs x15, S3_4_C3_C1_4
 mrs x10,  HDFGWTR_EL2
+// CHECK-INST: mrs x10, HDFGWTR_EL2
+// CHECK-ENCODING: encoding: [0xaa,0x31,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register
+// CHECK-UNKNOWN:  d53c31aa      mrs x10, S3_4_C3_C1_5
 mrs x5,   HAFGRTR_EL2
-// CHECK: mrs     x30, HFGRTR_EL2         // encoding: [0x9e,0x11,0x3c,0xd5]
-// CHECK: mrs     x25, HFGWTR_EL2         // encoding: [0xb9,0x11,0x3c,0xd5]
-// CHECK: mrs     x20, HFGITR_EL2         // encoding: [0xd4,0x11,0x3c,0xd5]
-// CHECK: mrs     x15, HDFGRTR_EL2        // encoding: [0x8f,0x31,0x3c,0xd5]
-// CHECK: mrs     x10, HDFGWTR_EL2        // encoding: [0xaa,0x31,0x3c,0xd5]
-// CHECK: mrs     x5, HAFGRTR_EL2         // encoding: [0xc5,0x31,0x3c,0xd5]
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
+// CHECK-INST: mrs x5, HAFGRTR_EL2
+// CHECK-ENCODING: encoding: [0xc5,0x31,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register
+// CHECK-UNKNOWN:  d53c31c5      mrs x5, S3_4_C3_C1_6
 
 
 mrs x3, HDFGRTR2_EL2
+// CHECK-INST: mrs x3, HDFGRTR2_EL2
+// CHECK-ENCODING: encoding: [0x03,0x31,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:9: error: expected readable system register
+// CHECK-UNKNOWN:  d53c3103      mrs x3, S3_4_C3_C1_0
 mrs x3, HDFGWTR2_EL2
+// CHECK-INST: mrs x3, HDFGWTR2_EL2
+// CHECK-ENCODING: encoding: [0x23,0x31,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:9: error: expected readable system register
+// CHECK-UNKNOWN:  d53c3123      mrs x3, S3_4_C3_C1_1
 mrs x3, HFGRTR2_EL2
+// CHECK-INST: mrs x3, HFGRTR2_EL2
+// CHECK-ENCODING: encoding: [0x43,0x31,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:9: error: expected readable system register
+// CHECK-UNKNOWN:  d53c3143      mrs x3, S3_4_C3_C1_2
 mrs x3, HFGWTR2_EL2
+// CHECK-INST: mrs x3, HFGWTR2_EL2
+// CHECK-ENCODING: encoding: [0x63,0x31,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:9: error: expected readable system register
+// CHECK-UNKNOWN:  d53c3163      mrs x3, S3_4_C3_C1_3
 mrs x3, HFGITR2_EL2
-// CHECK: mrs     x3, HDFGRTR2_EL2                // encoding: [0x03,0x31,0x3c,0xd5]
-// CHECK: mrs     x3, HDFGWTR2_EL2                // encoding: [0x23,0x31,0x3c,0xd5]
-// CHECK: mrs     x3, HFGRTR2_EL2                 // encoding: [0x43,0x31,0x3c,0xd5]
-// CHECK: mrs     x3, HFGWTR2_EL2                 // encoding: [0x63,0x31,0x3c,0xd5]
-// CHECK: mrs     x3, HFGITR2_EL2                 // encoding: [0xe3,0x31,0x3c,0xd5]
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
+// CHECK-INST: mrs x3, HFGITR2_EL2
+// CHECK-ENCODING: encoding: [0xe3,0x31,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:9: error: expected readable system register
+// CHECK-UNKNOWN:  d53c31e3      mrs x3, S3_4_C3_C1_7
 
 
 msr HDFGRTR2_EL2, x3
+// CHECK-INST: msr HDFGRTR2_EL2, x3
+// CHECK-ENCODING: encoding: [0x03,0x31,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c3103      msr S3_4_C3_C1_0, x3
 msr HDFGWTR2_EL2, x3
+// CHECK-INST: msr HDFGWTR2_EL2, x3
+// CHECK-ENCODING: encoding: [0x23,0x31,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c3123      msr S3_4_C3_C1_1, x3
 msr HFGRTR2_EL2, x3
+// CHECK-INST: msr HFGRTR2_EL2, x3
+// CHECK-ENCODING: encoding: [0x43,0x31,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c3143      msr S3_4_C3_C1_2, x3
 msr HFGWTR2_EL2, x3
+// CHECK-INST: msr HFGWTR2_EL2, x3
+// CHECK-ENCODING: encoding: [0x63,0x31,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c3163      msr S3_4_C3_C1_3, x3
 msr HFGITR2_EL2, x3
-// CHECK: msr     HDFGRTR2_EL2, x3                // encoding: [0x03,0x31,0x1c,0xd5]
-// CHECK: msr     HDFGWTR2_EL2, x3                // encoding: [0x23,0x31,0x1c,0xd5]
-// CHECK: msr     HFGRTR2_EL2, x3                 // encoding: [0x43,0x31,0x1c,0xd5]
-// CHECK: msr     HFGWTR2_EL2, x3                 // encoding: [0x63,0x31,0x1c,0xd5]
-// CHECK: msr     HFGITR2_EL2, x3                 // encoding: [0xe3,0x31,0x1c,0xd5]
-// NOFGT: error: expected writable system register
-// NOFGT: error: expected writable system register
-// NOFGT: error: expected writable system register
-// NOFGT: error: expected writable system register
-// NOFGT: error: expected writable system register
+// CHECK-INST: msr HFGITR2_EL2, x3
+// CHECK-ENCODING: encoding: [0xe3,0x31,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c31e3      msr S3_4_C3_C1_7, x3
diff --git a/llvm/test/MC/AArch64/armv8.8a-mops-diagnostics.s b/llvm/test/MC/AArch64/armv8.8a-mops-diagnostics.s
new file mode 100644
index 0000000000000..a9a8612bc048f
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv8.8a-mops-diagnostics.s
@@ -0,0 +1,227 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mops,+mte < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.8a,+mte < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+
+// All operand must be different from each other
+
+// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same
+cpyfp [x0]!, [x0]!, x1!
+cpyfp [x0]!, [x1]!, x0!
+cpyfp [x1]!, [x0]!, x0!
+
+// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same
+cpyfm [x0]!, [x0]!, x1!
+cpyfm [x0]!, [x1]!, x0!
+cpyfm [x1]!, [x0]!, x0!
+
+// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same
+cpyfe [x0]!, [x0]!, x1!
+cpyfe [x0]!, [x1]!, x0!
+cpyfe [x1]!, [x0]!, x0!
+
+// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same
+cpyp [x0]!, [x0]!, x1!
+cpyp [x0]!, [x1]!, x0!
+cpyp [x1]!, [x0]!, x0!
+
+// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same
+cpym [x0]!, [x0]!, x1!
+cpym [x0]!, [x1]!, x0!
+cpym [x1]!, [x0]!, x0!
+
+// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same
+cpye [x0]!, [x0]!, x1!
+cpye [x0]!, [x1]!, x0!
+cpye [x1]!, [x0]!, x0!
+
+// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same
+setp [x0]!, x0!, x1
+setp [x0]!, x1!, x0
+setp [x1]!, x0!, x0
+
+// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same
+setm [x0]!, x0!, x1
+setm [x0]!, x1!, x0
+setm [x1]!, x0!, x0
+
+// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same
+sete [x0]!, x0!, x1
+sete [x0]!, x1!, x0
+sete [x1]!, x0!, x0
+
+// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same
+setgp [x0]!, x0!, x1
+setgp [x0]!, x1!, x0
+setgp [x1]!, x0!, x0
+
+// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same
+setgm [x0]!, x0!, x1
+setgm [x0]!, x1!, x0
+setgm [x1]!, x0!, x0
+
+// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same
+setge [x0]!, x0!, x1
+setge [x0]!, x1!, x0
+setge [x1]!, x0!, x0
+
+// SP cannot be used as argument at any position
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpyfp [sp]!, [x1]!, x2!
+cpyfp [x0]!, [sp]!, x2!
+cpyfp [x0]!, [x1]!, sp!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpyfm [sp]!, [x1]!, x2!
+cpyfm [x0]!, [sp]!, x2!
+cpyfm [x0]!, [x1]!, sp!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpyfe [sp]!, [x1]!, x2!
+cpyfe [x0]!, [sp]!, x2!
+cpyfe [x0]!, [x1]!, sp!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpyp [sp]!, [x2]!, x2!
+cpyp [x0]!, [sp]!, x2!
+cpyp [x0]!, [x1]!, sp!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpym [sp]!, [x2]!, x2!
+cpym [x0]!, [sp]!, x2!
+cpym [x0]!, [x1]!, sp!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpye [sp]!, [x2]!, x2!
+cpye [x0]!, [sp]!, x2!
+cpye [x0]!, [x1]!, sp!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+setp [sp]!, x1!, x2
+setp [x0]!, sp!, x2
+setp [x0]!, x1!, sp
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+setm [sp]!, x1!, x2
+setm [x0]!, sp!, x2
+setm [x0]!, x1!, sp
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+sete [sp]!, x1!, x2
+sete [x0]!, sp!, x2
+sete [x0]!, x1!, sp
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+setgp [sp]!, x1!, x2
+setgp [x0]!, sp!, x2
+setgp [x0]!, x1!, sp
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+setgm [sp]!, x1!, x2
+setgm [x0]!, sp!, x2
+setgm [x0]!, x1!, sp
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+setge [sp]!, x1!, x2
+setge [x0]!, sp!, x2
+setge [x0]!, x1!, sp
+
+// XZR can only be used at:
+//  - the size operand in CPY.
+//  - the size or source operands in SET.
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpyfp [xzr]!, [x1]!, x2!
+cpyfp [x0]!, [xzr]!, x2!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpyfm [xzr]!, [x1]!, x2!
+cpyfm [x0]!, [xzr]!, x2!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpyfe [xzr]!, [x1]!, x2!
+cpyfe [x0]!, [xzr]!, x2!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpyp [xzr]!, [x2]!, x2!
+cpyp [x0]!, [xzr]!, x2!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpym [xzr]!, [x2]!, x2!
+cpym [x0]!, [xzr]!, x2!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpye [xzr]!, [x2]!, x2!
+cpye [x0]!, [xzr]!, x2!
+
+// CHECK-ERROR: error: invalid operand for instruction
+setp [xzr]!, x1!, x2
+
+// CHECK-ERROR: error: invalid operand for instruction
+setm [xzr]!, x1!, x2
+
+// CHECK-ERROR: error: invalid operand for instruction
+sete [xzr]!, x1!, x2
+
+// CHECK-ERROR: error: invalid operand for instruction
+setgp [xzr]!, x1!, x2
+
+// CHECK-ERROR: error: invalid operand for instruction
+setgm [xzr]!, x1!, x2
+
+// CHECK-ERROR: error: invalid operand for instruction
+setge [xzr]!, x1!, x2
diff --git a/llvm/test/MC/AArch64/armv8.8a-mops.s b/llvm/test/MC/AArch64/armv8.8a-mops.s
index f8d75e73d47d5..45064a98c6b9b 100644
--- a/llvm/test/MC/AArch64/armv8.8a-mops.s
+++ b/llvm/test/MC/AArch64/armv8.8a-mops.s
@@ -1,654 +1,735 @@
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mops,+mte < %s 2> %t | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MTE
-// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.8a,+mte < %s 2> %t | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MTE
-// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mops < %s 2> %t | FileCheck %s --check-prefix=CHECK
-// RUN: FileCheck --check-prefix=CHECK-NO-MTE-ERR %s < %t
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.8a < %s 2> %t | FileCheck %s --check-prefix=CHECK
-// RUN: FileCheck --check-prefix=CHECK-NO-MTE-ERR %s < %t
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
-// RUN: FileCheck --check-prefix=CHECK-NO-MOPS-ERR --check-prefix=CHECK-NO-MOPSMTE-ERR %s < %t
+// RUN: llvm-mc -triple=aarch64 -show-encoding -m...
[truncated]

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llvmbot commented Jun 30, 2025

@llvm/pr-subscribers-mc

Author: Jonathan Thackray (jthackray)

Changes

This is a series of patches (3/4) to unify assembly/disassembly of recent AArch64 tests into a single file. The aim is to improve consistency, so that all instructions and system registers are thoroughly tested, and future test cases will be in a unified format.

This patch:

  • removes .txt tests which have multiple feature dependancies
  • makes the .s tests have a roundabout run line to test both encoding and assembly
  • creates diagnostic tests when needed

Patch is 461.48 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/146330.diff

29 Files Affected:

  • (modified) llvm/test/MC/AArch64/armv8.6a-fgt.s (+105-47)
  • (added) llvm/test/MC/AArch64/armv8.8a-mops-diagnostics.s (+227)
  • (modified) llvm/test/MC/AArch64/armv8.8a-mops.s (+569-488)
  • (modified) llvm/test/MC/AArch64/armv8.9a-clrbhb.s (+29-16)
  • (modified) llvm/test/MC/AArch64/armv8.9a-debug-pmu.s (+1560-467)
  • (modified) llvm/test/MC/AArch64/armv8.9a-lrcpc3.s (+237-138)
  • (modified) llvm/test/MC/AArch64/armv8.9a-specres2.s (+27-8)
  • (added) llvm/test/MC/AArch64/armv8.9a-the-diagnostics.s (+103)
  • (modified) llvm/test/MC/AArch64/armv8.9a-the.s (+677-572)
  • (added) llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s (+30)
  • (modified) llvm/test/MC/AArch64/armv9-mrrs.s (+235-92)
  • (added) llvm/test/MC/AArch64/armv9-msrr-diagnostics.s (+30)
  • (modified) llvm/test/MC/AArch64/armv9-msrr.s (+125-95)
  • (added) llvm/test/MC/AArch64/armv9-sysp-diagnostics.s (+35)
  • (removed) llvm/test/MC/AArch64/armv9-sysp.s (-538)
  • (modified) llvm/test/MC/AArch64/armv9.4a-chk.s (+26-9)
  • (modified) llvm/test/MC/AArch64/armv9.5a-tlbiw.s (+38-15)
  • (added) llvm/test/MC/AArch64/armv9a-sysp.s (+834)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt (-75)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv8.8a-mops.txt (-434)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv8.9a-clrbhb.txt (-16)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv8.9a-debug-pmu.txt (-730)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt (-113)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv8.9a-specres2.txt (-16)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv8.9a-the.txt (-482)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv9-sysp.txt (-562)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv9-sysreg128.txt (-147)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv9.4a-chk.txt (-8)
  • (removed) llvm/test/MC/Disassembler/AArch64/armv9.5a-tlbiw.txt (-27)
diff --git a/llvm/test/MC/AArch64/armv8.6a-fgt.s b/llvm/test/MC/AArch64/armv8.6a-fgt.s
index 11002aca5e1a0..4b825ea191a68 100644
--- a/llvm/test/MC/AArch64/armv8.6a-fgt.s
+++ b/llvm/test/MC/AArch64/armv8.6a-fgt.s
@@ -1,75 +1,133 @@
-// RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+fgt   < %s | FileCheck %s
-// RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+v8.6a < %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64 -show-encoding  < %s 2>&1         | FileCheck %s --check-prefix=NOFGT
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v8.6a < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fgt < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fgt < %s \
+// RUN:        | llvm-objdump -d --mattr=+fgt - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fgt < %s \
+// RUN:   | llvm-objdump -d --mattr=-fgt - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fgt < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+fgt -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
 
 msr HFGRTR_EL2, x0
+// CHECK-INST: msr HFGRTR_EL2, x0
+// CHECK-ENCODING: encoding: [0x80,0x11,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c1180      msr S3_4_C1_C1_4, x0
 msr HFGWTR_EL2, x5
+// CHECK-INST: msr HFGWTR_EL2, x5
+// CHECK-ENCODING: encoding: [0xa5,0x11,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c11a5      msr S3_4_C1_C1_5, x5
 msr HFGITR_EL2, x10
+// CHECK-INST: msr HFGITR_EL2, x10
+// CHECK-ENCODING: encoding: [0xca,0x11,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c11ca      msr S3_4_C1_C1_6, x10
 msr HDFGRTR_EL2, x15
+// CHECK-INST: msr HDFGRTR_EL2, x15
+// CHECK-ENCODING: encoding: [0x8f,0x31,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c318f      msr S3_4_C3_C1_4, x15
 msr HDFGWTR_EL2, x20
+// CHECK-INST: msr HDFGWTR_EL2, x20
+// CHECK-ENCODING: encoding: [0xb4,0x31,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c31b4      msr S3_4_C3_C1_5, x20
 msr HAFGRTR_EL2, x25
-// CHECK: msr     HFGRTR_EL2, x0          // encoding: [0x80,0x11,0x1c,0xd5]
-// CHECK: msr     HFGWTR_EL2, x5          // encoding: [0xa5,0x11,0x1c,0xd5]
-// CHECK: msr     HFGITR_EL2, x10         // encoding: [0xca,0x11,0x1c,0xd5]
-// CHECK: msr     HDFGRTR_EL2, x15        // encoding: [0x8f,0x31,0x1c,0xd5]
-// CHECK: msr     HDFGWTR_EL2, x20        // encoding: [0xb4,0x31,0x1c,0xd5]
-// CHECK: msr     HAFGRTR_EL2, x25        // encoding: [0xd9,0x31,0x1c,0xd5]
-// NOFGT: error: expected writable system register or pstate
-// NOFGT: error: expected writable system register or pstate
-// NOFGT: error: expected writable system register or pstate
-// NOFGT: error: expected writable system register or pstate
-// NOFGT: error: expected writable system register or pstate
-// NOFGT: error: expected writable system register or pstate
+// CHECK-INST: msr HAFGRTR_EL2, x25
+// CHECK-ENCODING: encoding: [0xd9,0x31,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c31d9      msr S3_4_C3_C1_6, x25
 
 mrs x30,  HFGRTR_EL2
+// CHECK-INST: mrs x30, HFGRTR_EL2
+// CHECK-ENCODING: encoding: [0x9e,0x11,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register
+// CHECK-UNKNOWN:  d53c119e      mrs x30, S3_4_C1_C1_4
 mrs x25,  HFGWTR_EL2
+// CHECK-INST: mrs x25, HFGWTR_EL2
+// CHECK-ENCODING: encoding: [0xb9,0x11,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register
+// CHECK-UNKNOWN:  d53c11b9      mrs x25, S3_4_C1_C1_5
 mrs x20,  HFGITR_EL2
+// CHECK-INST: mrs x20, HFGITR_EL2
+// CHECK-ENCODING: encoding: [0xd4,0x11,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register
+// CHECK-UNKNOWN:  d53c11d4      mrs x20, S3_4_C1_C1_6
 mrs x15,  HDFGRTR_EL2
+// CHECK-INST: mrs x15, HDFGRTR_EL2
+// CHECK-ENCODING: encoding: [0x8f,0x31,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register
+// CHECK-UNKNOWN:  d53c318f      mrs x15, S3_4_C3_C1_4
 mrs x10,  HDFGWTR_EL2
+// CHECK-INST: mrs x10, HDFGWTR_EL2
+// CHECK-ENCODING: encoding: [0xaa,0x31,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register
+// CHECK-UNKNOWN:  d53c31aa      mrs x10, S3_4_C3_C1_5
 mrs x5,   HAFGRTR_EL2
-// CHECK: mrs     x30, HFGRTR_EL2         // encoding: [0x9e,0x11,0x3c,0xd5]
-// CHECK: mrs     x25, HFGWTR_EL2         // encoding: [0xb9,0x11,0x3c,0xd5]
-// CHECK: mrs     x20, HFGITR_EL2         // encoding: [0xd4,0x11,0x3c,0xd5]
-// CHECK: mrs     x15, HDFGRTR_EL2        // encoding: [0x8f,0x31,0x3c,0xd5]
-// CHECK: mrs     x10, HDFGWTR_EL2        // encoding: [0xaa,0x31,0x3c,0xd5]
-// CHECK: mrs     x5, HAFGRTR_EL2         // encoding: [0xc5,0x31,0x3c,0xd5]
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
+// CHECK-INST: mrs x5, HAFGRTR_EL2
+// CHECK-ENCODING: encoding: [0xc5,0x31,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register
+// CHECK-UNKNOWN:  d53c31c5      mrs x5, S3_4_C3_C1_6
 
 
 mrs x3, HDFGRTR2_EL2
+// CHECK-INST: mrs x3, HDFGRTR2_EL2
+// CHECK-ENCODING: encoding: [0x03,0x31,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:9: error: expected readable system register
+// CHECK-UNKNOWN:  d53c3103      mrs x3, S3_4_C3_C1_0
 mrs x3, HDFGWTR2_EL2
+// CHECK-INST: mrs x3, HDFGWTR2_EL2
+// CHECK-ENCODING: encoding: [0x23,0x31,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:9: error: expected readable system register
+// CHECK-UNKNOWN:  d53c3123      mrs x3, S3_4_C3_C1_1
 mrs x3, HFGRTR2_EL2
+// CHECK-INST: mrs x3, HFGRTR2_EL2
+// CHECK-ENCODING: encoding: [0x43,0x31,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:9: error: expected readable system register
+// CHECK-UNKNOWN:  d53c3143      mrs x3, S3_4_C3_C1_2
 mrs x3, HFGWTR2_EL2
+// CHECK-INST: mrs x3, HFGWTR2_EL2
+// CHECK-ENCODING: encoding: [0x63,0x31,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:9: error: expected readable system register
+// CHECK-UNKNOWN:  d53c3163      mrs x3, S3_4_C3_C1_3
 mrs x3, HFGITR2_EL2
-// CHECK: mrs     x3, HDFGRTR2_EL2                // encoding: [0x03,0x31,0x3c,0xd5]
-// CHECK: mrs     x3, HDFGWTR2_EL2                // encoding: [0x23,0x31,0x3c,0xd5]
-// CHECK: mrs     x3, HFGRTR2_EL2                 // encoding: [0x43,0x31,0x3c,0xd5]
-// CHECK: mrs     x3, HFGWTR2_EL2                 // encoding: [0x63,0x31,0x3c,0xd5]
-// CHECK: mrs     x3, HFGITR2_EL2                 // encoding: [0xe3,0x31,0x3c,0xd5]
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
-// NOFGT: error: expected readable system register
+// CHECK-INST: mrs x3, HFGITR2_EL2
+// CHECK-ENCODING: encoding: [0xe3,0x31,0x3c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:9: error: expected readable system register
+// CHECK-UNKNOWN:  d53c31e3      mrs x3, S3_4_C3_C1_7
 
 
 msr HDFGRTR2_EL2, x3
+// CHECK-INST: msr HDFGRTR2_EL2, x3
+// CHECK-ENCODING: encoding: [0x03,0x31,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c3103      msr S3_4_C3_C1_0, x3
 msr HDFGWTR2_EL2, x3
+// CHECK-INST: msr HDFGWTR2_EL2, x3
+// CHECK-ENCODING: encoding: [0x23,0x31,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c3123      msr S3_4_C3_C1_1, x3
 msr HFGRTR2_EL2, x3
+// CHECK-INST: msr HFGRTR2_EL2, x3
+// CHECK-ENCODING: encoding: [0x43,0x31,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c3143      msr S3_4_C3_C1_2, x3
 msr HFGWTR2_EL2, x3
+// CHECK-INST: msr HFGWTR2_EL2, x3
+// CHECK-ENCODING: encoding: [0x63,0x31,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c3163      msr S3_4_C3_C1_3, x3
 msr HFGITR2_EL2, x3
-// CHECK: msr     HDFGRTR2_EL2, x3                // encoding: [0x03,0x31,0x1c,0xd5]
-// CHECK: msr     HDFGWTR2_EL2, x3                // encoding: [0x23,0x31,0x1c,0xd5]
-// CHECK: msr     HFGRTR2_EL2, x3                 // encoding: [0x43,0x31,0x1c,0xd5]
-// CHECK: msr     HFGWTR2_EL2, x3                 // encoding: [0x63,0x31,0x1c,0xd5]
-// CHECK: msr     HFGITR2_EL2, x3                 // encoding: [0xe3,0x31,0x1c,0xd5]
-// NOFGT: error: expected writable system register
-// NOFGT: error: expected writable system register
-// NOFGT: error: expected writable system register
-// NOFGT: error: expected writable system register
-// NOFGT: error: expected writable system register
+// CHECK-INST: msr HFGITR2_EL2, x3
+// CHECK-ENCODING: encoding: [0xe3,0x31,0x1c,0xd5]
+// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate
+// CHECK-UNKNOWN:  d51c31e3      msr S3_4_C3_C1_7, x3
diff --git a/llvm/test/MC/AArch64/armv8.8a-mops-diagnostics.s b/llvm/test/MC/AArch64/armv8.8a-mops-diagnostics.s
new file mode 100644
index 0000000000000..a9a8612bc048f
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv8.8a-mops-diagnostics.s
@@ -0,0 +1,227 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mops,+mte < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.8a,+mte < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+
+// All operand must be different from each other
+
+// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same
+cpyfp [x0]!, [x0]!, x1!
+cpyfp [x0]!, [x1]!, x0!
+cpyfp [x1]!, [x0]!, x0!
+
+// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same
+cpyfm [x0]!, [x0]!, x1!
+cpyfm [x0]!, [x1]!, x0!
+cpyfm [x1]!, [x0]!, x0!
+
+// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same
+cpyfe [x0]!, [x0]!, x1!
+cpyfe [x0]!, [x1]!, x0!
+cpyfe [x1]!, [x0]!, x0!
+
+// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same
+cpyp [x0]!, [x0]!, x1!
+cpyp [x0]!, [x1]!, x0!
+cpyp [x1]!, [x0]!, x0!
+
+// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same
+cpym [x0]!, [x0]!, x1!
+cpym [x0]!, [x1]!, x0!
+cpym [x1]!, [x0]!, x0!
+
+// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same
+cpye [x0]!, [x0]!, x1!
+cpye [x0]!, [x1]!, x0!
+cpye [x1]!, [x0]!, x0!
+
+// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same
+setp [x0]!, x0!, x1
+setp [x0]!, x1!, x0
+setp [x1]!, x0!, x0
+
+// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same
+setm [x0]!, x0!, x1
+setm [x0]!, x1!, x0
+setm [x1]!, x0!, x0
+
+// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same
+sete [x0]!, x0!, x1
+sete [x0]!, x1!, x0
+sete [x1]!, x0!, x0
+
+// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same
+setgp [x0]!, x0!, x1
+setgp [x0]!, x1!, x0
+setgp [x1]!, x0!, x0
+
+// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same
+setgm [x0]!, x0!, x1
+setgm [x0]!, x1!, x0
+setgm [x1]!, x0!, x0
+
+// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same
+// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same
+// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same
+setge [x0]!, x0!, x1
+setge [x0]!, x1!, x0
+setge [x1]!, x0!, x0
+
+// SP cannot be used as argument at any position
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpyfp [sp]!, [x1]!, x2!
+cpyfp [x0]!, [sp]!, x2!
+cpyfp [x0]!, [x1]!, sp!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpyfm [sp]!, [x1]!, x2!
+cpyfm [x0]!, [sp]!, x2!
+cpyfm [x0]!, [x1]!, sp!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpyfe [sp]!, [x1]!, x2!
+cpyfe [x0]!, [sp]!, x2!
+cpyfe [x0]!, [x1]!, sp!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpyp [sp]!, [x2]!, x2!
+cpyp [x0]!, [sp]!, x2!
+cpyp [x0]!, [x1]!, sp!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpym [sp]!, [x2]!, x2!
+cpym [x0]!, [sp]!, x2!
+cpym [x0]!, [x1]!, sp!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpye [sp]!, [x2]!, x2!
+cpye [x0]!, [sp]!, x2!
+cpye [x0]!, [x1]!, sp!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+setp [sp]!, x1!, x2
+setp [x0]!, sp!, x2
+setp [x0]!, x1!, sp
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+setm [sp]!, x1!, x2
+setm [x0]!, sp!, x2
+setm [x0]!, x1!, sp
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+sete [sp]!, x1!, x2
+sete [x0]!, sp!, x2
+sete [x0]!, x1!, sp
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+setgp [sp]!, x1!, x2
+setgp [x0]!, sp!, x2
+setgp [x0]!, x1!, sp
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+setgm [sp]!, x1!, x2
+setgm [x0]!, sp!, x2
+setgm [x0]!, x1!, sp
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+setge [sp]!, x1!, x2
+setge [x0]!, sp!, x2
+setge [x0]!, x1!, sp
+
+// XZR can only be used at:
+//  - the size operand in CPY.
+//  - the size or source operands in SET.
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpyfp [xzr]!, [x1]!, x2!
+cpyfp [x0]!, [xzr]!, x2!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpyfm [xzr]!, [x1]!, x2!
+cpyfm [x0]!, [xzr]!, x2!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpyfe [xzr]!, [x1]!, x2!
+cpyfe [x0]!, [xzr]!, x2!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpyp [xzr]!, [x2]!, x2!
+cpyp [x0]!, [xzr]!, x2!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpym [xzr]!, [x2]!, x2!
+cpym [x0]!, [xzr]!, x2!
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+cpye [xzr]!, [x2]!, x2!
+cpye [x0]!, [xzr]!, x2!
+
+// CHECK-ERROR: error: invalid operand for instruction
+setp [xzr]!, x1!, x2
+
+// CHECK-ERROR: error: invalid operand for instruction
+setm [xzr]!, x1!, x2
+
+// CHECK-ERROR: error: invalid operand for instruction
+sete [xzr]!, x1!, x2
+
+// CHECK-ERROR: error: invalid operand for instruction
+setgp [xzr]!, x1!, x2
+
+// CHECK-ERROR: error: invalid operand for instruction
+setgm [xzr]!, x1!, x2
+
+// CHECK-ERROR: error: invalid operand for instruction
+setge [xzr]!, x1!, x2
diff --git a/llvm/test/MC/AArch64/armv8.8a-mops.s b/llvm/test/MC/AArch64/armv8.8a-mops.s
index f8d75e73d47d5..45064a98c6b9b 100644
--- a/llvm/test/MC/AArch64/armv8.8a-mops.s
+++ b/llvm/test/MC/AArch64/armv8.8a-mops.s
@@ -1,654 +1,735 @@
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mops,+mte < %s 2> %t | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MTE
-// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.8a,+mte < %s 2> %t | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MTE
-// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mops < %s 2> %t | FileCheck %s --check-prefix=CHECK
-// RUN: FileCheck --check-prefix=CHECK-NO-MTE-ERR %s < %t
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.8a < %s 2> %t | FileCheck %s --check-prefix=CHECK
-// RUN: FileCheck --check-prefix=CHECK-NO-MTE-ERR %s < %t
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
-// RUN: FileCheck --check-prefix=CHECK-NO-MOPS-ERR --check-prefix=CHECK-NO-MOPSMTE-ERR %s < %t
+// RUN: llvm-mc -triple=aarch64 -show-encoding -m...
[truncated]

This was referenced Jun 30, 2025
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tmatheson-arm reviewed Jun 30, 2025
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llvm/test/MC/AArch64/armv8.9a-clrbhb.s Outdated
// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8.8a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9.3a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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@tmatheson-arm tmatheson-arm Jun 30, 2025

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Why keeping a different test format for CLRBHB?

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@jthackray jthackray Jun 30, 2025

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I'm not sure (Virginia converted this file) but I suspect because it has fairly extensive version-dependent tests at the top.

llvm/test/MC/AArch64/armv8.9a-the.s
rcwcasp x0, x1, x6, x7, [x4]
// CHECK: rcwcasp x0, x1, x6, x7, [x4] // encoding: [0x86,0x0c,0x20,0x19]
// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
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ERROR-NO-D128 tests seem to be missing

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@jthackray jthackray Jun 30, 2025

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Thanks, re-added.

@jthackray jthackray force-pushed the users/jthackray/unify-tests2 branch from 40dca64 to 9b48b94 Compare June 30, 2025 16:22
@jthackray jthackray force-pushed the users/jthackray/unify-tests3 branch from d2b3c5b to 0909842 Compare June 30, 2025 16:22
@jthackray jthackray force-pushed the users/jthackray/unify-tests2 branch from 9b48b94 to 17e13b2 Compare June 30, 2025 18:05
@jthackray jthackray force-pushed the users/jthackray/unify-tests3 branch from 0909842 to aec7816 Compare June 30, 2025 18:05
@jthackray jthackray force-pushed the users/jthackray/unify-tests2 branch from 3e81a94 to af93d1b Compare July 24, 2025 23:12
@jthackray jthackray force-pushed the users/jthackray/unify-tests3 branch from aec7816 to 59e7365 Compare July 24, 2025 23:12
@jthackray jthackray force-pushed the users/jthackray/unify-tests2 branch from af93d1b to ede81b8 Compare August 6, 2025 15:20
@jthackray jthackray force-pushed the users/jthackray/unify-tests3 branch from 59e7365 to 119f50d Compare August 6, 2025 15:21
jthackray added a commit that referenced this pull request Aug 13, 2025
@jthackray @virginia-cangelosi
[AArch64][llvm] Unify AArch64 tests into a single file (1/4) (NFC) (#…
69452d5 
…146328)

This is a series of patches (1/4) to unify assembly/disassembly of
recent AArch64 tests into a single file. The aim is to improve
consistency, so that all instructions and system registers are
thoroughly tested, and future test cases will be in a unified format.

This patch:
 * unifies errorless .s and .txt tests into a single file
 * remove .txt tests which don't have feature requirements
* makes the .s tests have a roundabout run line to test both encoding
and assembly
 
See also #146329, #146330 and #146331.

---------

Co-authored-by: Virginia Cangelosi <[email protected]>
@jthackray jthackray force-pushed the users/jthackray/unify-tests2 branch from ede81b8 to 7c9180b Compare August 13, 2025 12:48
Base automatically changed from users/jthackray/unify-tests2 to main August 13, 2025 13:39
jthackray added a commit that referenced this pull request Aug 13, 2025
@jthackray @virginia-cangelosi
[AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) (#…
b878793 
…146329)

This is a series of patches (2/4) to unify assembly/disassembly of
recent AArch64 tests into a single file. The aim is to improve
consistency, so that all instructions and system registers are
thoroughly tested, and future test cases will be in a unified format.

This patch:
 * removes .txt tests which have only one feature required
* makes the .s tests have a roundabout run line to test both encoding
and assembly
 * creates diagnostic tests when needed
 * fixes naming convention of tests
 
See also #146328, #146330 and #146331.

Co-authored-by: Virginia Cangelosi <[email protected]>
@jthackray @virginia-cangelosi
[AArch64][llvm] Unify AArch64 tests into a single file (3/4) (NFC)
0d1fdcb 
This is a series of patches (3/4) to unify assembly/disassembly of
recent AArch64 tests into a single file. The aim is to improve
consistency, so that all instructions and system registers are
thoroughly tested, and future test cases will be in a unified format.

This patch:
 * removes .txt tests which have multiple feature dependancies
 * makes the .s tests have a roundabout run line to test both encoding and assembly
 * creates diagnostic tests when needed

Co-authored-by: Virginia Cangelosi <[email protected]>
@jthackray jthackray force-pushed the users/jthackray/unify-tests3 branch from 119f50d to 0d1fdcb Compare August 13, 2025 13:42
@jthackray jthackray enabled auto-merge (squash) August 13, 2025 13:42
@jthackray jthackray merged commit 8453f20 into main Aug 13, 2025
9 checks passed
@jthackray jthackray deleted the users/jthackray/unify-tests3 branch August 13, 2025 14:07
jthackray added a commit that referenced this pull request Aug 13, 2025
@jthackray @virginia-cangelosi
[AArch64][llvm] Unify AArch64 tests into a single file (4/4) (NFC) (#…
7bd0c5f 
…146331)

This is a series of patches (4/4) to unify assembly/disassembly of
recent AArch64 tests into a single file. The aim is to improve
consistency, so that all instructions and system registers are
thoroughly tested, and future test cases will be in a unified format.

This patch:
 * removes .txt tests whose .s tests have functions
* makes the .s tests have a roundabout run line to test both encoding
and assembly

See also #146328, #146329 and #146330.

Co-authored-by: Virginia Cangelosi <[email protected]>
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@tmatheson-arm tmatheson-arm tmatheson-arm left review comments

@CarolineConcatto CarolineConcatto CarolineConcatto approved these changes

@kmclaughlin-arm kmclaughlin-arm Awaiting requested review from kmclaughlin-arm

@Lukacma Lukacma Awaiting requested review from Lukacma

@amilendra amilendra Awaiting requested review from amilendra

@virginia-cangelosi virginia-cangelosi Awaiting requested review from virginia-cangelosi

@rgwott rgwott Awaiting requested review from rgwott

@pratlucas pratlucas Awaiting requested review from pratlucas

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@jthackray @llvmbot @CarolineConcatto @tmatheson-arm