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5 changes: 3 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1768,8 +1768,9 @@ void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
SlotIndex NewDefSI =
LIS->InsertMachineInstrInMaps(*ReadVLMI).getRegSlot();
LiveInterval &DefLI = LIS->getInterval(VLOutput);
VNInfo *DefVNI = DefLI.getVNInfoAt(DefLI.beginIndex());
DefLI.removeSegment(DefLI.beginIndex(), NewDefSI);
LiveRange::Segment *DefSeg = DefLI.getSegmentContaining(NewDefSI);
VNInfo *DefVNI = DefLI.getVNInfoAt(DefSeg->start);
DefLI.removeSegment(DefSeg->start, NewDefSI);
DefVNI->def = NewDefSI;
}
}
Expand Down
32 changes: 32 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
Original file line number Diff line number Diff line change
Expand Up @@ -722,3 +722,35 @@ define i64 @avl_undef2() {
%1 = tail call i64 @llvm.riscv.vsetvli(i64 poison, i64 2, i64 7)
ret i64 %1
}

define i64 @vsetvli_vleff(ptr %s, i64 %evl) {
; CHECK-LABEL: vsetvli_vleff:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: .LBB37_1: # %while.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vle16ff.v v9, (a0)
; CHECK-NEXT: csrr a2, vl
; CHECK-NEXT: beqz a2, .LBB37_1
; CHECK-NEXT: # %bb.2: # %while.end
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ret
entry:
br label %while.cond

while.cond:
%new_vl.0 = phi i64 [ 0, %entry ], [ %1, %while.body ]
%cmp = icmp eq i64 %new_vl.0, 0
br i1 %cmp, label %while.body, label %while.end

while.body:
%0 = tail call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> zeroinitializer, ptr %s, i64 %evl)
%1 = extractvalue { <vscale x 4 x i16>, i64 } %0, 1
br label %while.cond

while.end:
ret i64 0
}
53 changes: 53 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
Original file line number Diff line number Diff line change
Expand Up @@ -100,6 +100,18 @@
ret void
}

define i64 @vsetvli_vleff() {
bb0:
br i1 poison, label %bb1, label %bb2
bb1:
%0 = tail call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> zeroinitializer, ptr null, i64 0)
%1 = extractvalue { <vscale x 4 x i16>, i64 } %0, 1
br label %bb2
bb2:
%x8 = phi i64 [%1, %bb1], [0, %bb0]
ret i64 %x8
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Suggested change
bb0:
br i1 poison, label %bb1, label %bb2
bb1:
%0 = tail call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> zeroinitializer, ptr null, i64 0)
%1 = extractvalue { <vscale x 4 x i16>, i64 } %0, 1
br label %bb2
bb2:
%x8 = phi i64 [%1, %bb1], [0, %bb0]
ret i64 %x8
ret void

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}

declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1

declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>, ptr nocapture, i64) #4
Expand Down Expand Up @@ -622,3 +634,44 @@ body: |
dead $x0 = PseudoVSETIVLI 1, 208, implicit-def $vl, implicit-def $vtype
%v:vr = COPY $v8, implicit $vtype
%x = PseudoVSETVLI %x, 208, implicit-def $vl, implicit-def $vtype
...
---
name: vsetvli_vleff
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: vsetvli_vleff
; CHECK: bb.0.bb0:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: BNE $x0, $x0, %bb.2
; CHECK-NEXT: PseudoBR %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.bb1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 200 /* e16, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: renamable $v8 = PseudoVMV_V_I_M1 undef renamable $v8, 0, -1, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 136 /* e16, m1, tu, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: dead renamable $v8, $x0 = PseudoVLE16FF_V_M1 killed renamable $v8, $x0, 0, 4 /* e16 */, 2 /* tu, ma */, implicit-def dead $vl, implicit $vl, implicit $vtype :: (load unknown-size from `ptr null`, align 2)
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = PseudoReadVL implicit $vl
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.bb2:
; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit killed $x10
bb.0.bb0:
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bb.0.bb0:
bb.0:

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Addressed

successors: %bb.1(0x40000000), %bb.2(0x40000000)

%9:gpr = COPY $x0
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Suggested change
%9:gpr = COPY $x0
%vl:gpr = COPY $x0

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Addressed

BNE $x0, $x0, %bb.2
PseudoBR %bb.1

bb.1.bb1:
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bb.1.bb1:
bb.1:

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successors: %bb.2(0x80000000)

renamable $v8 = PseudoVMV_V_I_M1 undef renamable $v8, 0, -1, 4 /* e16 */, 0 /* tu, mu */
dead renamable $v8, %9:gpr = PseudoVLE16FF_V_M1 killed renamable $v8, $x0, 0, 4 /* e16 */, 2 /* tu, ma */, implicit-def dead $vl :: (load unknown-size from `ptr null`, align 2)
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renamable $v8 = PseudoVMV_V_I_M1 undef renamable $v8, 0, -1, 4 /* e16 */, 0 /* tu, mu */
dead renamable $v8, %9:gpr = PseudoVLE16FF_V_M1 killed renamable $v8, $x0, 0, 4 /* e16 */, 2 /* tu, ma */, implicit-def dead $vl :: (load unknown-size from `ptr null`, align 2)
$noreg, %vl:gpr = PseudoVLE16FF_V_M1 $noreg, $noreg, 0, 4 /* e16 */, 2 /* tu, ma */

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Addressed


bb.2.bb2:
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bb.2.bb2:
bb.2:

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Addressed

$x10 = COPY %9
PseudoRET implicit killed $x10
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$x10 = COPY %9
PseudoRET implicit killed $x10
$x10 = COPY %vl
PseudoRET implicit killed $x10

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