Skip to content

[DAG] foldABSToABD - fallback to value tracking if the (ABS (SUB LHS, RHS)) operands aren't extended #147053

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Jul 6, 2025
Merged

[DAG] foldABSToABD - fallback to value tracking if the (ABS (SUB LHS, RHS)) operands aren't extended #147053

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
abc561d
[DAG] foldABSToABD - fallback to value tracking if the (ABS (SUB LHS,…
RKSimon Jul 4, 2025
a7f55bd
Merge branch 'main' into dag-abd-valuetracking
RKSimon Jul 5, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
15 changes: 11 additions & 4 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11402,18 +11402,25 @@ SDValue DAGCombiner::foldABSToABD(SDNode *N, const SDLoc &DL) {
SDValue AbsOp0 = N->getOperand(0);
unsigned Opc0 = Op0.getOpcode();

// Check if the operands of the sub are (zero|sign)-extended.
// TODO: Should we use ValueTracking instead?
// Check if the operands of the sub are (zero|sign)-extended, otherwise
// fallback to ValueTracking.
if (Opc0 != Op1.getOpcode() ||
(Opc0 != ISD::ZERO_EXTEND && Opc0 != ISD::SIGN_EXTEND &&
Opc0 != ISD::SIGN_EXTEND_INREG)) {
// fold (abs (sub nsw x, y)) -> abds(x, y)
// Don't fold this for unsupported types as we lose the NSW handling.
if (AbsOp0->getFlags().hasNoSignedWrap() && hasOperation(ISD::ABDS, VT) &&
TLI.preferABDSToABSWithNSW(VT)) {
if (hasOperation(ISD::ABDS, VT) && TLI.preferABDSToABSWithNSW(VT) &&
(AbsOp0->getFlags().hasNoSignedWrap() ||
DAG.willNotOverflowSub(/*IsSigned=*/true, Op0, Op1))) {
SDValue ABD = DAG.getNode(ISD::ABDS, DL, VT, Op0, Op1);
return DAG.getZExtOrTrunc(ABD, DL, SrcVT);
}
// fold (abs (sub x, y)) -> abdu(x, y)
if (hasOperation(ISD::ABDU, VT) && DAG.SignBitIsZero(Op0) &&
DAG.SignBitIsZero(Op1)) {
SDValue ABD = DAG.getNode(ISD::ABDU, DL, VT, Op0, Op1);
return DAG.getZExtOrTrunc(ABD, DL, SrcVT);
}
return SDValue();
}

Expand Down
53 changes: 20 additions & 33 deletions llvm/test/CodeGen/AArch64/abd-combine.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -18,13 +18,11 @@ define <8 x i16> @abdu_const(<8 x i16> %src1) {
; CHECK-LABEL: abdu_const:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: ushll2 v2.4s, v0.8h, #0
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: sub v1.4s, v2.4s, v1.4s
; CHECK-NEXT: abs v1.4s, v1.4s
; CHECK-NEXT: abs v0.4s, v0.4s
; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h
; CHECK-NEXT: ushll v2.4s, v0.4h, #0
; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0
; CHECK-NEXT: uabd v0.4s, v0.4s, v1.4s
; CHECK-NEXT: uabd v1.4s, v2.4s, v1.4s
; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h
; CHECK-NEXT: ret
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
%sub = sub <8 x i32> %zextsrc1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
Expand All @@ -37,10 +35,10 @@ define <8 x i16> @abdu_const_lhs(<8 x i16> %src1) {
; CHECK-LABEL: abdu_const_lhs:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: usubw v2.4s, v1.4s, v0.4h
; CHECK-NEXT: usubw2 v0.4s, v1.4s, v0.8h
; CHECK-NEXT: abs v0.4s, v0.4s
; CHECK-NEXT: abs v1.4s, v2.4s
; CHECK-NEXT: ushll v2.4s, v0.4h, #0
; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0
; CHECK-NEXT: uabd v0.4s, v0.4s, v1.4s
; CHECK-NEXT: uabd v1.4s, v2.4s, v1.4s
; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h
; CHECK-NEXT: ret
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
Expand All @@ -53,13 +51,6 @@ define <8 x i16> @abdu_const_lhs(<8 x i16> %src1) {
define <8 x i16> @abdu_const_zero(<8 x i16> %src1) {
; CHECK-LABEL: abdu_const_zero:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: ushll v2.4s, v0.4h, #0
; CHECK-NEXT: usubw2 v0.4s, v1.4s, v0.8h
; CHECK-NEXT: neg v1.4s, v2.4s
; CHECK-NEXT: abs v0.4s, v0.4s
; CHECK-NEXT: abs v1.4s, v1.4s
; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h
; CHECK-NEXT: ret
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
%sub = sub <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, %zextsrc1
Expand Down Expand Up @@ -328,13 +319,11 @@ define <8 x i16> @abds_const(<8 x i16> %src1) {
; CHECK-LABEL: abds_const:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: sshll2 v2.4s, v0.8h, #0
; CHECK-NEXT: sshll v0.4s, v0.4h, #0
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: sub v1.4s, v2.4s, v1.4s
; CHECK-NEXT: abs v1.4s, v1.4s
; CHECK-NEXT: abs v0.4s, v0.4s
; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h
; CHECK-NEXT: sshll v2.4s, v0.4h, #0
; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0
; CHECK-NEXT: sabd v0.4s, v0.4s, v1.4s
; CHECK-NEXT: sabd v1.4s, v2.4s, v1.4s
; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h
; CHECK-NEXT: ret
%zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%sub = sub <8 x i32> %zextsrc1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
Expand All @@ -347,10 +336,10 @@ define <8 x i16> @abds_const_lhs(<8 x i16> %src1) {
; CHECK-LABEL: abds_const_lhs:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: ssubw v2.4s, v1.4s, v0.4h
; CHECK-NEXT: ssubw2 v0.4s, v1.4s, v0.8h
; CHECK-NEXT: abs v0.4s, v0.4s
; CHECK-NEXT: abs v1.4s, v2.4s
; CHECK-NEXT: sshll v2.4s, v0.4h, #0
; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0
; CHECK-NEXT: sabd v0.4s, v0.4s, v1.4s
; CHECK-NEXT: sabd v1.4s, v2.4s, v1.4s
; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h
; CHECK-NEXT: ret
%zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
Expand All @@ -363,10 +352,8 @@ define <8 x i16> @abds_const_lhs(<8 x i16> %src1) {
define <8 x i16> @abds_const_zero(<8 x i16> %src1) {
; CHECK-LABEL: abds_const_zero:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: sshll v2.4s, v0.4h, #0
; CHECK-NEXT: ssubw2 v0.4s, v1.4s, v0.8h
; CHECK-NEXT: neg v1.4s, v2.4s
; CHECK-NEXT: sshll v1.4s, v0.4h, #0
; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0
; CHECK-NEXT: abs v0.4s, v0.4s
; CHECK-NEXT: abs v1.4s, v1.4s
; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AArch64/sve-abd.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -283,8 +283,7 @@ define <vscale x 4 x i32> @uabd_non_matching_promotion(<vscale x 4 x i8> %a, <vs
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: and z0.s, z0.s, #0xff
; CHECK-NEXT: sxtb z1.s, p0/m, z1.s
; CHECK-NEXT: sub z0.s, z0.s, z1.s
; CHECK-NEXT: abs z0.s, p0/m, z0.s
; CHECK-NEXT: sabd z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: ret
%a.zext = zext <vscale x 4 x i8> %a to <vscale x 4 x i32>
%b.zext = sext <vscale x 4 x i8> %b to <vscale x 4 x i32>
Expand Down
10 changes: 4 additions & 6 deletions llvm/test/CodeGen/RISCV/rvv/abd.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -316,12 +316,10 @@ define <vscale x 4 x i32> @uabd_non_matching_promotion(<vscale x 4 x i8> %a, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vzext.vf4 v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vsext.vf2 v8, v9
; CHECK-NEXT: vwsub.wv v10, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vrsub.vi v8, v10, 0
; CHECK-NEXT: vmax.vv v8, v10, v8
; CHECK-NEXT: vsext.vf4 v12, v9
; CHECK-NEXT: vmin.vv v8, v10, v12
; CHECK-NEXT: vmax.vv v10, v10, v12
; CHECK-NEXT: vsub.vv v8, v10, v8
; CHECK-NEXT: ret
%a.zext = zext <vscale x 4 x i8> %a to <vscale x 4 x i32>
%b.zext = sext <vscale x 4 x i8> %b to <vscale x 4 x i32>
Expand Down
Loading