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@RKSimon RKSimon commented Jul 4, 2025

Lets us remove all the horrible commutative handling

Lets us remove all the horrible commutative handling
@RKSimon RKSimon requested a review from topperc July 4, 2025 15:29
@llvmbot llvmbot added the llvm:SelectionDAG SelectionDAGISel as well label Jul 4, 2025
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llvmbot commented Jul 4, 2025

@llvm/pr-subscribers-llvm-selectiondag

Author: Simon Pilgrim (RKSimon)

Changes

Lets us remove all the horrible commutative handling


Full diff: https://github.com/llvm/llvm-project/pull/147079.diff

1 Files Affected:

  • (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+5-9)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 55f994f357b75..3daa65d3cb324 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10001,15 +10001,11 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
 
   // fold Y = sra (X, size(X)-1); xor (add (X, Y), Y) -> (abs X)
   if (!LegalOperations || hasOperation(ISD::ABS, VT)) {
-    SDValue A = N0Opcode == ISD::ADD ? N0 : N1;
-    SDValue S = N0Opcode == ISD::SRA ? N0 : N1;
-    if (A.getOpcode() == ISD::ADD && S.getOpcode() == ISD::SRA) {
-      SDValue A0 = A.getOperand(0), A1 = A.getOperand(1);
-      SDValue S0 = S.getOperand(0);
-      if ((A0 == S && A1 == S0) || (A1 == S && A0 == S0))
-        if (ConstantSDNode *C = isConstOrConstSplat(S.getOperand(1)))
-          if (C->getAPIntValue() == (VT.getScalarSizeInBits() - 1))
-            return DAG.getNode(ISD::ABS, DL, VT, S0);
+    SDValue X, Y;
+    if (sd_match(N, m_Xor(m_Add(m_Value(X), m_Value(Y)), m_Deferred(Y))) &&
+        sd_match(Y, m_Sra(m_Specific(X),
+                          m_SpecificInt(VT.getScalarSizeInBits() - 1)))) {
+      return DAG.getNode(ISD::ABS, DL, VT, X);
     }
   }
 

@RKSimon RKSimon closed this Jul 4, 2025
@RKSimon RKSimon deleted the dag-abs-sdpatternmatch branch July 7, 2025 11:32
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2 participants