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[DAGCombine] Change isBuildVectorAll* -> isConstantSplatVectorAll* for Vselect #147305

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Merged
merged 4 commits into from
Jul 11, 2025
Merged

[DAGCombine] Change isBuildVectorAll* -> isConstantSplatVectorAll* for Vselect #147305

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a9d15d1
[DAGCombine] Precommit test for isConstantSplatVectorAll
badumbatish Jul 7, 2025
1ad59c0
[DAGCombine] Use isConstantSplatVectorAll in VSelect
badumbatish Jul 9, 2025
7500bfc
Move tests to simd-select, fix nits
badumbatish Jul 10, 2025
363cd6a
Merge branch 'main' into bitselect_v128_zero_simpl
RKSimon Jul 11, 2025
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8 changes: 4 additions & 4 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -13091,10 +13091,10 @@ static SDValue combineVSelectWithAllOnesOrZeros(SDValue Cond, SDValue TVal,
EVT CondVT = Cond.getValueType();
assert(CondVT.isVector() && "Vector select expects a vector selector!");

bool IsTAllZero = ISD::isBuildVectorAllZeros(TVal.getNode());
bool IsTAllOne = ISD::isBuildVectorAllOnes(TVal.getNode());
bool IsFAllZero = ISD::isBuildVectorAllZeros(FVal.getNode());
bool IsFAllOne = ISD::isBuildVectorAllOnes(FVal.getNode());
bool IsTAllZero = ISD::isConstantSplatVectorAllZeros(TVal.getNode());
bool IsTAllOne = ISD::isConstantSplatVectorAllOnes(TVal.getNode());
bool IsFAllZero = ISD::isConstantSplatVectorAllZeros(FVal.getNode());
bool IsFAllOne = ISD::isConstantSplatVectorAllOnes(FVal.getNode());

// no vselect(cond, 0/-1, X) or vselect(cond, X, 0/-1), return
if (!IsTAllZero && !IsTAllOne && !IsFAllZero && !IsFAllOne)
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12 changes: 4 additions & 8 deletions llvm/test/CodeGen/WebAssembly/fpclamptosat_vec.ll
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Expand Up @@ -107,11 +107,9 @@ define <2 x i32> @ustest_f64i32(<2 x double> %x) {
; CHECK-NEXT: v128.bitselect
; CHECK-NEXT: local.tee 0
; CHECK-NEXT: v128.const 0, 0
; CHECK-NEXT: local.tee 1
; CHECK-NEXT: local.get 0
; CHECK-NEXT: local.get 1
; CHECK-NEXT: i64x2.gt_s
; CHECK-NEXT: v128.bitselect
; CHECK-NEXT: local.get 0
; CHECK-NEXT: v128.and
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i8x16.shuffle 0, 1, 2, 3, 8, 9, 10, 11, 0, 1, 2, 3, 0, 1, 2, 3
; CHECK-NEXT: # fallthrough-return
Expand Down Expand Up @@ -1558,11 +1556,9 @@ define <2 x i32> @ustest_f64i32_mm(<2 x double> %x) {
; CHECK-NEXT: v128.bitselect
; CHECK-NEXT: local.tee 0
; CHECK-NEXT: v128.const 0, 0
; CHECK-NEXT: local.tee 1
; CHECK-NEXT: local.get 0
; CHECK-NEXT: local.get 1
; CHECK-NEXT: i64x2.gt_s
; CHECK-NEXT: v128.bitselect
; CHECK-NEXT: local.get 0
; CHECK-NEXT: v128.and
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i8x16.shuffle 0, 1, 2, 3, 8, 9, 10, 11, 0, 1, 2, 3, 0, 1, 2, 3
; CHECK-NEXT: # fallthrough-return
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70 changes: 70 additions & 0 deletions llvm/test/CodeGen/WebAssembly/simd-select.ll
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Expand Up @@ -552,3 +552,73 @@ define <2 x double> @select_eq_v2f64(i32 %i, <2 x double> %x, <2 x double> %y) {
%res = select i1 %c, <2 x double> %x, <2 x double> %y
ret <2 x double> %res
}

define <4 x i32> @select_splat_first_zero_and_icmp(<4 x i32> %x) {
; CHECK-LABEL: select_splat_first_zero_and_icmp:
; CHECK: .functype select_splat_first_zero_and_icmp (v128) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
; CHECK-NEXT: v128.const 2139095040, 2139095040, 2139095040, 2139095040
; CHECK-NEXT: v128.and
; CHECK-NEXT: v128.const 0, 0, 0, 0
; CHECK-NEXT: i32x4.ne
; CHECK-NEXT: local.get 0
; CHECK-NEXT: v128.and
; CHECK-NEXT: # fallthrough-return
%a = and <4 x i32> %x, splat (i32 2139095040)
%c = icmp eq <4 x i32> %a, zeroinitializer
%res = select <4 x i1> %c, <4 x i32> zeroinitializer, <4 x i32> %x
ret <4 x i32> %res
}

define <4 x i32> @select_splat_second_zero_and_icmp(<4 x i32> %x) {
; CHECK-LABEL: select_splat_second_zero_and_icmp:
; CHECK: .functype select_splat_second_zero_and_icmp (v128) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
; CHECK-NEXT: v128.const 2139095040, 2139095040, 2139095040, 2139095040
; CHECK-NEXT: v128.and
; CHECK-NEXT: v128.const 0, 0, 0, 0
; CHECK-NEXT: i32x4.eq
; CHECK-NEXT: local.get 0
; CHECK-NEXT: v128.and
; CHECK-NEXT: # fallthrough-return
%a = and <4 x i32> %x, splat (i32 2139095040)
%c = icmp eq <4 x i32> %a, zeroinitializer
%res = select <4 x i1> %c, <4 x i32> %x, <4 x i32> zeroinitializer
ret <4 x i32> %res
}

define <4 x i32> @select_splat_first_zero_cond_input(<4 x i1> %c, <4 x i32> %x) {
; CHECK-LABEL: select_splat_first_zero_cond_input:
; CHECK: .functype select_splat_first_zero_cond_input (v128, v128) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: v128.const 0, 0, 0, 0
; CHECK-NEXT: local.get 1
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const 31
; CHECK-NEXT: i32x4.shl
; CHECK-NEXT: i32.const 31
; CHECK-NEXT: i32x4.shr_s
; CHECK-NEXT: v128.bitselect
; CHECK-NEXT: # fallthrough-return
%res = select <4 x i1> %c, <4 x i32> zeroinitializer, <4 x i32> %x
ret <4 x i32> %res
}

define <4 x i32> @select_splat_second_zero_cond_input(<4 x i1> %c, <4 x i32> %x) {
; CHECK-LABEL: select_splat_second_zero_cond_input:
; CHECK: .functype select_splat_second_zero_cond_input (v128, v128) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const 31
; CHECK-NEXT: i32x4.shl
; CHECK-NEXT: i32.const 31
; CHECK-NEXT: i32x4.shr_s
; CHECK-NEXT: local.get 1
; CHECK-NEXT: v128.and
; CHECK-NEXT: # fallthrough-return
%res = select <4 x i1> %c, <4 x i32> %x, <4 x i32> zeroinitializer
ret <4 x i32> %res
}