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[AMDGPU] Inflate to %AV regclass #147413

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[AMDGPU] Inflate to %AV regclass #147413

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3f6ecaf
[AMDGPU] Inflate to %av regclass
jrbyrnes Jul 15, 2025
6d52737
Update lit tests
jrbyrnes Sep 26, 2025
f797b9b
Revert "Update lit tests"
jrbyrnes Oct 8, 2025
4dfc7ab
Control with flag
jrbyrnes Oct 8, 2025
896fb4b
Update llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp
jrbyrnes Oct 15, 2025
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25 changes: 25 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,12 @@ using namespace llvm;

#define DEBUG_TYPE "amdgpu-prepare-agpr-alloc"

static cl::opt<bool> InflateToAVClass(
"amdgpu-avgpr-inflation", cl::Hidden,
cl::desc("Whether to inflate register to the avgpr register "
"class -- which is assignable to either vgpr or agpr."),
cl::init(false));

namespace {

class AMDGPUPrepareAGPRAllocImpl {
Expand Down Expand Up @@ -97,6 +103,8 @@ bool AMDGPUPrepareAGPRAllocImpl::run(MachineFunction &MF) {

const MCInstrDesc &AVImmPseudo32 = TII.get(AMDGPU::AV_MOV_B32_IMM_PSEUDO);
const MCInstrDesc &AVImmPseudo64 = TII.get(AMDGPU::AV_MOV_B64_IMM_PSEUDO);
const SIRegisterInfo *TRI =
static_cast<const SIRegisterInfo *>(MRI.getTargetRegisterInfo());

bool Changed = false;
for (MachineBasicBlock &MBB : MF) {
Expand All @@ -119,6 +127,23 @@ bool AMDGPUPrepareAGPRAllocImpl::run(MachineFunction &MF) {
Changed = true;
continue;
}

if (!InflateToAVClass)
continue;

for (MachineOperand &Op : MI.operands()) {
if (!Op.isReg() || !Op.isDef())
continue;

Register DefReg = Op.getReg();
if (DefReg.isPhysical())
continue;

const TargetRegisterClass *RC = MRI.getRegClass(DefReg);

if (TRI->hasVectorRegisters(RC))
Changed |= MRI.recomputeRegClass(DefReg);
}
}
}

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