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[CodeGen] Do not use subsituteRegister to update implicit def #148068

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Merged
PeimingLiu merged 4 commits into from
Jul 11, 2025
Merged

[CodeGen] Do not use subsituteRegister to update implicit def #148068

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db3674a
[CodeGen] Do not use subsituteRegister to update implicit def
PeimingLiu Jul 10, 2025
7a347d8
add test
PeimingLiu Jul 11, 2025
5950e82
address comment
PeimingLiu Jul 11, 2025
df33a79
remove useless check
PeimingLiu Jul 11, 2025
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29 changes: 21 additions & 8 deletions llvm/lib/CodeGen/TargetInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -214,6 +214,24 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
Reg1.isPhysical() ? MI.getOperand(Idx1).isRenamable() : false;
bool Reg2IsRenamable =
Reg2.isPhysical() ? MI.getOperand(Idx2).isRenamable() : false;

// For a case like this:
// %0.sub = INST %0.sub(tied), %1.sub, implicit-def %0
// we need to update the implicit-def after commuting to result in:
// %1.sub = INST %1.sub(tied), %0.sub, implicit-def %1
SmallVector<unsigned> UpdateImplicitDefIdx;
if (HasDef && MI.hasImplicitDef()) {
const TargetRegisterInfo *TRI =
MI.getMF()->getSubtarget().getRegisterInfo();
for (auto [OpNo, MO] : llvm::enumerate(MI.implicit_operands())) {
Register ImplReg = MO.getReg();
if ((ImplReg.isVirtual() && ImplReg == Reg0) ||
(ImplReg.isPhysical() && Reg0.isPhysical() &&
TRI->isSubRegisterEq(ImplReg, Reg0)))
UpdateImplicitDefIdx.push_back(OpNo + MI.getNumExplicitOperands());
}
}

// If destination is tied to either of the commuted source register, then
// it must be updated.
if (HasDef && Reg0 == Reg1 &&
Expand All @@ -238,15 +256,10 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
}

if (HasDef) {
// Use `substituteRegister` so that for a case like this:
// %0.sub = INST %0.sub(tied), %1.sub, implicit-def %0
// the implicit-def is also updated, to result in:
// %1.sub = INST %1.sub(tied), %0.sub, implicit-def %1
const TargetRegisterInfo &TRI =
*MI.getMF()->getSubtarget().getRegisterInfo();
Register FromReg = CommutedMI->getOperand(0).getReg();
CommutedMI->substituteRegister(FromReg, Reg0, /*SubRegIdx=*/0, TRI);
CommutedMI->getOperand(0).setReg(Reg0);
CommutedMI->getOperand(0).setSubReg(SubReg0);
for (unsigned Idx : UpdateImplicitDefIdx)
CommutedMI->getOperand(Idx).setReg(Reg0);
}
CommutedMI->getOperand(Idx2).setReg(Reg1);
CommutedMI->getOperand(Idx1).setReg(Reg2);
Expand Down
21 changes: 21 additions & 0 deletions llvm/test/CodeGen/X86/coalesce-commutative-implicit-def.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -35,3 +35,24 @@ body: |
%0:gr64_with_sub_8bit = COPY %1:gr64_with_sub_8bit
RET 0, implicit %0
...
# Commuting instruction with 3 ops is handled correctly.
---
name: commuting_3_ops
tracksRegLiveness: true
body: |
bb.0:
liveins: $ymm0, $ymm1

; CHECK-LABEL: name: commuting_3_ops
; CHECK: liveins: $ymm0, $ymm1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr256 = contract nofpexcept VFMADD213PSYr [[COPY1]], [[COPY]], [[COPY]], implicit $mxcsr
; CHECK-NEXT: RET 0, implicit [[COPY1]]
%0:vr256 = COPY $ymm1
%1:vr256 = COPY $ymm0
%0:vr256 = contract nofpexcept VFMADD231PSYr %0:vr256, %0:vr256, %1:vr256, implicit $mxcsr
%1:vr256 = COPY %0:vr256
RET 0, implicit %1
...