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[RISCV] Support PreserveMost calling convention #148214

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Merged
wangpc-pp merged 8 commits into from
Jul 30, 2025
Merged

[RISCV] Support PreserveMost calling convention #148214

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7965e1e
[RISCV] Support PreserveMost calling convention
wangpc-pp Jul 11, 2025
901dbe4
Add E and getCallPreservedMask
wangpc-pp Jul 15, 2025
1b545dc
Update CSR list to exclude t1, t2 and t3
wangpc-pp Jul 28, 2025
f883418
Remove unnecessary include
wangpc-pp Jul 29, 2025
562d0a8
Show the save of clobbered registers
wangpc-pp Jul 29, 2025
2900358
Fix test
wangpc-pp Jul 30, 2025
237d6cc
Use CSR_Interrupt
wangpc-pp Jul 30, 2025
f006d10
Merge branch 'main' into main-riscv-preserve-most
wangpc-pp Jul 30, 2025
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2 changes: 2 additions & 0 deletions llvm/docs/LangRef.rst
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Expand Up @@ -413,6 +413,8 @@ added in the future:
- On AArch64 the callee preserves all general purpose registers, except
X0-X8 and X16-X18. Not allowed with ``nest``.

- On RISC-V the callee preserve x5-x31 except x6, x7 and x28 registers.

The idea behind this convention is to support calls to runtime functions
that have a hot path and a cold path. The hot path is usually a small piece
of code that doesn't use many registers. The cold path might need to call out to
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4 changes: 4 additions & 0 deletions llvm/lib/Target/RISCV/RISCVCallingConv.td
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Expand Up @@ -95,3 +95,7 @@ def CSR_XLEN_F32_V_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F32_V_Interrupt,
// Same as CSR_XLEN_F64_V_Interrupt, but excluding X16-X31.
def CSR_XLEN_F64_V_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F64_V_Interrupt,
(sequence "X%u", 16, 31))>;

def CSR_RT_MostRegs : CalleeSavedRegs<(sub CSR_Interrupt, X6, X7, X28)>;
def CSR_RT_MostRegs_RVE : CalleeSavedRegs<(sub CSR_RT_MostRegs,
(sequence "X%u", 16, 31))>;
1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Expand Up @@ -22455,6 +22455,7 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
case CallingConv::C:
case CallingConv::Fast:
case CallingConv::SPIR_KERNEL:
case CallingConv::PreserveMost:
case CallingConv::GRAAL:
case CallingConv::RISCV_VectorCall:
#define CC_VLS_CASE(ABI_VLEN) case CallingConv::RISCV_VLSCall_##ABI_VLEN:
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11 changes: 10 additions & 1 deletion llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
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Expand Up @@ -68,6 +68,9 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
if (MF->getFunction().getCallingConv() == CallingConv::GHC)
return CSR_NoRegs_SaveList;
if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost)
return Subtarget.hasStdExtE() ? CSR_RT_MostRegs_RVE_SaveList
: CSR_RT_MostRegs_SaveList;
if (MF->getFunction().hasFnAttribute("interrupt")) {
if (Subtarget.hasVInstructions()) {
if (Subtarget.hasStdExtD())
Expand Down Expand Up @@ -811,7 +814,13 @@ RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,

if (CC == CallingConv::GHC)
return CSR_NoRegs_RegMask;
switch (Subtarget.getTargetABI()) {
RISCVABI::ABI ABI = Subtarget.getTargetABI();
if (CC == CallingConv::PreserveMost) {
if (ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E)
return CSR_RT_MostRegs_RVE_RegMask;
return CSR_RT_MostRegs_RegMask;
}
switch (ABI) {
default:
llvm_unreachable("Unrecognized ABI");
case RISCVABI::ABI_ILP32E:
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