Skip to content

[DAG] visitFREEZE - enable SRA/SRL handling #148252

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
wants to merge 6 commits into from
Closed

[DAG] visitFREEZE - enable SRA/SRL handling #148252

Show file tree
Hide file tree
Changes from 2 commits
Commits
Show all changes
6 commits
Select commit Hold shift + click to select a range
8387d02
[DAG] visitFREEZE - enable SRA/SRL handling
RKSimon Jul 1, 2025
4d9fb58
Merge branch 'main' into dag-freeze-shift
RKSimon Jul 23, 2025
e71e5ce
Merge branch 'upstream' into dag-freeze-shift
RKSimon Aug 22, 2025
baada86
fix clang formatting screwed up in merge
RKSimon Aug 22, 2025
792f37b
regenerate updated tests
RKSimon Aug 22, 2025
febded4
Merge branch 'main' into dag-freeze-shift
RKSimon Aug 27, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 0 additions & 6 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -16726,12 +16726,6 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
if (DAG.isGuaranteedNotToBeUndefOrPoison(N0, /*PoisonOnly*/ false))
return N0;

// We currently avoid folding freeze over SRA/SRL, due to the problems seen
// with (freeze (assert ext)) blocking simplifications of SRA/SRL. See for
// example https://reviews.llvm.org/D136529#4120959.
if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)
return SDValue();

// Fold freeze(op(x, ...)) -> op(freeze(x), ...).
// Try to push freeze through instructions that propagate but don't produce
// poison as far as possible. If an operand of freeze follows three
Expand Down
14 changes: 6 additions & 8 deletions llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -14,15 +14,13 @@ define amdgpu_kernel void @uniform_trunc_i16_to_i1(ptr addrspace(1) %out, i16 %x
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[COPY2]], %subreg.sub0, killed [[COPY1]], %subreg.sub1, killed [[S_MOV_B32_1]], %subreg.sub2, killed [[S_MOV_B32_]], %subreg.sub3
; GCN-NEXT: [[S_SEXT_I32_I16_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I16 [[S_LOAD_DWORD_IMM]]
; GCN-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; GCN-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[S_LOAD_DWORD_IMM]], killed [[S_MOV_B32_2]], implicit-def dead $scc
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY killed [[S_LSHR_B32_]]
; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY3]], implicit-def dead $scc
; GCN-NEXT: S_CMP_EQ_U32 killed [[S_AND_B32_]], 1, implicit-def $scc
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY killed [[S_LOAD_DWORD_IMM]]
; GCN-NEXT: [[S_SEXT_I32_I16_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I16 [[COPY3]]
; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 65536, [[COPY3]], implicit-def dead $scc
; GCN-NEXT: S_CMP_LG_U32 killed [[S_AND_B32_]], 0, implicit-def $scc
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_64 = COPY $scc
; GCN-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GCN-NEXT: S_CMP_LT_I32 killed [[S_SEXT_I32_I16_]], killed [[S_MOV_B32_3]], implicit-def $scc
; GCN-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GCN-NEXT: S_CMP_LT_I32 killed [[S_SEXT_I32_I16_]], killed [[S_MOV_B32_2]], implicit-def $scc
; GCN-NEXT: [[COPY5:%[0-9]+]]:sreg_64 = COPY $scc
; GCN-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 killed [[COPY5]], killed [[COPY4]], implicit-def dead $scc
; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B64_]], implicit $exec
Expand Down
75 changes: 12 additions & 63 deletions llvm/test/CodeGen/AMDGPU/freeze.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5692,10 +5692,6 @@ define void @freeze_v3i16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX6-SDAG-NEXT: s_mov_b32 s5, s6
; GFX6-SDAG-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX6-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX6-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-SDAG-NEXT: v_or_b32_e32 v0, v0, v4
; GFX6-SDAG-NEXT: buffer_store_short v1, v[2:3], s[4:7], 0 addr64 offset:4
; GFX6-SDAG-NEXT: buffer_store_dword v0, v[2:3], s[4:7], 0 addr64
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0)
Expand Down Expand Up @@ -5725,10 +5721,6 @@ define void @freeze_v3i16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX7-SDAG-NEXT: s_mov_b32 s5, s6
; GFX7-SDAG-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v0, v4
; GFX7-SDAG-NEXT: buffer_store_short v1, v[2:3], s[4:7], 0 addr64 offset:4
; GFX7-SDAG-NEXT: buffer_store_dword v0, v[2:3], s[4:7], 0 addr64
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -6351,10 +6343,6 @@ define void @freeze_v3f16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX6-SDAG-NEXT: s_mov_b32 s5, s6
; GFX6-SDAG-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX6-SDAG-NEXT: v_and_b32_e32 v4, 0xffff, v0
; GFX6-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX6-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-SDAG-NEXT: v_or_b32_e32 v0, v4, v0
; GFX6-SDAG-NEXT: buffer_store_short v1, v[2:3], s[4:7], 0 addr64 offset:4
; GFX6-SDAG-NEXT: buffer_store_dword v0, v[2:3], s[4:7], 0 addr64
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0)
Expand Down Expand Up @@ -6384,10 +6372,6 @@ define void @freeze_v3f16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX7-SDAG-NEXT: s_mov_b32 s5, s6
; GFX7-SDAG-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: v_and_b32_e32 v4, 0xffff, v0
; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX7-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v4, v0
; GFX7-SDAG-NEXT: buffer_store_short v1, v[2:3], s[4:7], 0 addr64 offset:4
; GFX7-SDAG-NEXT: buffer_store_dword v0, v[2:3], s[4:7], 0 addr64
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -12355,14 +12339,9 @@ define void @freeze_v3i8(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX6-SDAG-NEXT: s_mov_b32 s5, s6
; GFX6-SDAG-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX6-SDAG-NEXT: v_lshrrev_b32_e32 v4, 8, v0
; GFX6-SDAG-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX6-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX6-SDAG-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX6-SDAG-NEXT: v_or_b32_e32 v0, v0, v4
; GFX6-SDAG-NEXT: buffer_store_byte v1, v[2:3], s[4:7], 0 addr64 offset:2
; GFX6-SDAG-NEXT: buffer_store_short v0, v[2:3], s[4:7], 0 addr64
; GFX6-SDAG-NEXT: buffer_store_byte v1, v[2:3], s[4:7], 0 addr64 offset:2
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
;
Expand Down Expand Up @@ -12400,14 +12379,9 @@ define void @freeze_v3i8(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX7-SDAG-NEXT: s_mov_b32 s5, s6
; GFX7-SDAG-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v4, 8, v0
; GFX7-SDAG-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-SDAG-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v0, v4
; GFX7-SDAG-NEXT: buffer_store_byte v1, v[2:3], s[4:7], 0 addr64 offset:2
; GFX7-SDAG-NEXT: buffer_store_short v0, v[2:3], s[4:7], 0 addr64
; GFX7-SDAG-NEXT: buffer_store_byte v1, v[2:3], s[4:7], 0 addr64 offset:2
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
Expand Down Expand Up @@ -12482,11 +12456,7 @@ define void @freeze_v3i8(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: global_load_dword v0, v[0:1], off
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX10-SDAG-NEXT: v_lshrrev_b16 v1, 8, v0
; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX10-SDAG-NEXT: v_lshlrev_b16 v1, 8, v1
; GFX10-SDAG-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-SDAG-NEXT: global_store_byte v[2:3], v4, off offset:2
; GFX10-SDAG-NEXT: global_store_byte_d16_hi v[2:3], v0, off offset:2
; GFX10-SDAG-NEXT: global_store_short v[2:3], v0, off
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
Expand All @@ -12507,36 +12477,15 @@ define void @freeze_v3i8(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX10-GISEL-NEXT: global_store_byte_d16_hi v[2:3], v0, off offset:2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: freeze_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: global_load_b32 v1, v[0:1], off
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.h, 0
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b16 v0.l, 8, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.h
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_clause 0x1
; GFX11-SDAG-TRUE16-NEXT: global_store_b8 v[2:3], v4, off offset:2
; GFX11-SDAG-TRUE16-NEXT: global_store_b16 v[2:3], v0, off
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: freeze_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b16 v1, 8, v0
; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v0
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1
; GFX11-SDAG-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
; GFX11-SDAG-FAKE16-NEXT: s_clause 0x1
; GFX11-SDAG-FAKE16-NEXT: global_store_b8 v[2:3], v0, off offset:2
; GFX11-SDAG-FAKE16-NEXT: global_store_b16 v[2:3], v1, off
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-SDAG-LABEL: freeze_v3i8:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX11-SDAG-NEXT: s_clause 0x1
; GFX11-SDAG-NEXT: global_store_d16_hi_b8 v[2:3], v0, off offset:2
; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: freeze_v3i8:
; GFX11-GISEL: ; %bb.0:
Expand Down
40 changes: 20 additions & 20 deletions llvm/test/CodeGen/AMDGPU/srem64.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -653,11 +653,11 @@ define i64 @v_test_srem24_64(i64 %x, i64 %y) {
define amdgpu_kernel void @s_test_srem25_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_srem25_64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s0, s[4:5], 0xe
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i32 s0, s0, 7
; GCN-NEXT: s_ashr_i32 s0, s1, 7
; GCN-NEXT: s_abs_i32 s8, s0
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
Expand Down Expand Up @@ -694,11 +694,11 @@ define amdgpu_kernel void @s_test_srem25_64(ptr addrspace(1) %out, i64 %x, i64 %
;
; GCN-IR-LABEL: s_test_srem25_64:
; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_load_dword s0, s[4:5], 0xe
; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_ashr_i32 s0, s0, 7
; GCN-IR-NEXT: s_ashr_i32 s0, s1, 7
; GCN-IR-NEXT: s_abs_i32 s8, s0
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
Expand Down Expand Up @@ -742,11 +742,11 @@ define amdgpu_kernel void @s_test_srem25_64(ptr addrspace(1) %out, i64 %x, i64 %
define amdgpu_kernel void @s_test_srem31_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_srem31_64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s0, s[4:5], 0xe
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i32 s0, s0, 1
; GCN-NEXT: s_ashr_i32 s0, s1, 1
; GCN-NEXT: s_abs_i32 s8, s0
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
Expand Down Expand Up @@ -783,11 +783,11 @@ define amdgpu_kernel void @s_test_srem31_64(ptr addrspace(1) %out, i64 %x, i64 %
;
; GCN-IR-LABEL: s_test_srem31_64:
; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_load_dword s0, s[4:5], 0xe
; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_ashr_i32 s0, s0, 1
; GCN-IR-NEXT: s_ashr_i32 s0, s1, 1
; GCN-IR-NEXT: s_abs_i32 s8, s0
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
Expand Down Expand Up @@ -832,11 +832,11 @@ define amdgpu_kernel void @s_test_srem31_64(ptr addrspace(1) %out, i64 %x, i64 %
define amdgpu_kernel void @s_test_srem32_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_srem32_64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s0, s[4:5], 0xe
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_abs_i32 s8, s0
; GCN-NEXT: s_abs_i32 s8, s1
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
; GCN-NEXT: s_sub_i32 s0, 0, s8
; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
Expand Down Expand Up @@ -871,11 +871,11 @@ define amdgpu_kernel void @s_test_srem32_64(ptr addrspace(1) %out, i64 %x, i64 %
;
; GCN-IR-LABEL: s_test_srem32_64:
; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_load_dword s0, s[4:5], 0xe
; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_abs_i32 s8, s0
; GCN-IR-NEXT: s_abs_i32 s8, s1
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8
; GCN-IR-NEXT: s_sub_i32 s0, 0, s8
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0
Expand Down Expand Up @@ -1053,25 +1053,25 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-IR-LABEL: s_test_srem33_64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; GCN-IR-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
; GCN-IR-NEXT: s_mov_b32 s13, 0
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 31
; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[4:5], 31
; GCN-IR-NEXT: s_ashr_i32 s4, s3, 31
; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[2:3], 31
; GCN-IR-NEXT: s_mov_b32 s5, s4
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
; GCN-IR-NEXT: s_ashr_i64 s[10:11], s[8:9], 31
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[6:7], s[4:5]
; GCN-IR-NEXT: s_sub_u32 s6, s2, s4
; GCN-IR-NEXT: s_subb_u32 s7, s3, s4
; GCN-IR-NEXT: s_ashr_i32 s2, s9, 31
; GCN-IR-NEXT: s_mov_b32 s3, s2
; GCN-IR-NEXT: s_xor_b64 s[8:9], s[8:9], s[2:3]
; GCN-IR-NEXT: s_xor_b64 s[8:9], s[10:11], s[2:3]
; GCN-IR-NEXT: s_sub_u32 s8, s8, s2
; GCN-IR-NEXT: s_subb_u32 s9, s9, s2
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[2:3], s[8:9], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[2:3], s[6:7], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[8:9], 0
; GCN-IR-NEXT: s_flbit_i32_b64 s12, s[8:9]
; GCN-IR-NEXT: s_or_b64 s[10:11], s[2:3], s[10:11]
; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[2:3]
; GCN-IR-NEXT: s_flbit_i32_b64 s20, s[6:7]
; GCN-IR-NEXT: s_sub_u32 s14, s12, s20
; GCN-IR-NEXT: s_subb_u32 s15, 0, 0
Expand Down
15 changes: 9 additions & 6 deletions llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -210,7 +210,8 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: slli a2, a1, 16
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: srliw a1, a1, 24
; RV64I-NEXT: slli a1, a1, 34
; RV64I-NEXT: srli a1, a1, 58
; RV64I-NEXT: xori a1, a1, 31
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: or a0, a0, a1
Expand Down Expand Up @@ -239,17 +240,19 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64I-NEXT: srliw a0, a0, 1
; RV64I-NEXT: beqz a0, .LBB4_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: srliw a2, a0, 2
; RV64I-NEXT: srli a2, a0, 2
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 4
; RV64I-NEXT: srli a2, a0, 4
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 8
; RV64I-NEXT: slli a2, a0, 33
; RV64I-NEXT: srli a2, a2, 41
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 16
; RV64I-NEXT: slli a2, a0, 33
; RV64I-NEXT: srli a2, a2, 49
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a2, a0, 1
Expand Down
15 changes: 9 additions & 6 deletions llvm/test/CodeGen/RISCV/rv64zbb.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -204,7 +204,8 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: slli a2, a1, 16
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: srliw a1, a1, 24
; RV64I-NEXT: slli a1, a1, 34
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I spent some time with this yesterday. The issue is that we don't push the freeze up the pairs of slli+add. I was able to trick it a bit by emitting a freeze before the slli+add pairs are emitted in expandCTPOP.

; RV64I-NEXT: srli a1, a1, 58
; RV64I-NEXT: xori a1, a1, 31
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: or a0, a0, a1
Expand All @@ -231,17 +232,19 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64I-NEXT: srliw a0, a0, 1
; RV64I-NEXT: beqz a0, .LBB4_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: srliw a2, a0, 2
; RV64I-NEXT: srli a2, a0, 2
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 4
; RV64I-NEXT: srli a2, a0, 4
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 8
; RV64I-NEXT: slli a2, a0, 33
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think the issue here is that we moved a freeze in the entry block which allowed computeKnownBits to compute a value for the output of the block. Then an AssertZExt was emitted in the the cond.false block. This allowed us to remove some bits from the AND mask and our isel code for srliw doesn't use computeKnownBits to fill in missing bits.

; RV64I-NEXT: srli a2, a2, 41
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 16
; RV64I-NEXT: slli a2, a0, 33
; RV64I-NEXT: srli a2, a2, 49
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a2, a0, 1
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -13,22 +13,22 @@ define void @vec3_setcc_crash(ptr %in, ptr %out) {
; RV32: # %bb.0:
; RV32-NEXT: lw a0, 0(a0)
; RV32-NEXT: srli a2, a0, 16
; RV32-NEXT: slli a3, a0, 16
; RV32-NEXT: slli a4, a0, 24
; RV32-NEXT: slli a5, a0, 8
; RV32-NEXT: srli a6, a3, 24
; RV32-NEXT: srai a3, a3, 24
; RV32-NEXT: srli a3, a0, 8
; RV32-NEXT: slli a4, a0, 16
; RV32-NEXT: slli a5, a0, 24
; RV32-NEXT: slli a6, a0, 8
; RV32-NEXT: srai a4, a4, 24
; RV32-NEXT: srai a5, a5, 24
; RV32-NEXT: srai a6, a6, 24
; RV32-NEXT: sgtz a6, a6
; RV32-NEXT: sgtz a5, a5
; RV32-NEXT: sgtz a4, a4
; RV32-NEXT: sgtz a3, a3
; RV32-NEXT: neg a3, a3
; RV32-NEXT: neg a4, a4
; RV32-NEXT: neg a5, a5
; RV32-NEXT: and a3, a3, a6
; RV32-NEXT: and a0, a4, a0
; RV32-NEXT: and a2, a5, a2
; RV32-NEXT: neg a6, a6
; RV32-NEXT: and a3, a4, a3
; RV32-NEXT: and a0, a5, a0
; RV32-NEXT: and a2, a6, a2
; RV32-NEXT: slli a3, a3, 8
; RV32-NEXT: zext.b a0, a0
; RV32-NEXT: or a0, a0, a3
Expand Down
Loading
Loading