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18 changes: 18 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
Original file line number Diff line number Diff line change
Expand Up @@ -1638,6 +1638,24 @@ def : CompressPat<(QC_E_ADDAI X2, simm10_lsb0000nonzero:$imm),
(C_ADDI16SP X2, simm10_lsb0000nonzero:$imm)>;
def : CompressPat<(QC_E_ADDI X2, X2, simm10_lsb0000nonzero:$imm),
(C_ADDI16SP X2, simm10_lsb0000nonzero:$imm)>;

def : CompressPat<(QC_E_ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm),
(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>;
def : CompressPat<(QC_E_ANDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm),
(ANDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>;
def : CompressPat<(QC_E_ORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm),
(ORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>;
def : CompressPat<(QC_E_XORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm),
(XORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>;

def : CompressPat<(QC_E_ADDAI GPRNoX0:$rd, simm12:$imm),
(ADDI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
def : CompressPat<(QC_E_ANDAI GPRNoX0:$rd, simm12:$imm),
(ANDI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
def : CompressPat<(QC_E_ORAI GPRNoX0:$rd, simm12:$imm),
(ORI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
def : CompressPat<(QC_E_XORAI GPRNoX0:$rd, simm12:$imm),
(XORI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
} // let isCompressOnly = true, Predicates = [HasVendorXqcilia, IsRV32]

let Predicates = [HasVendorXqciac, IsRV32] in {
Expand Down
40 changes: 40 additions & 0 deletions llvm/test/MC/RISCV/xqcilia-valid.s
Original file line number Diff line number Diff line change
Expand Up @@ -123,3 +123,43 @@ qc.e.addai x2, 48
# CHECK-NOALIAS: c.andi s1, -1
# CHECK-ENC: encoding: [0xfd,0x98]
qc.e.andai x9, 4294967295

# CHECK-ALIAS: addi t0, t2, 400
# CHECK-NOALIAS: addi t0, t2, 400
# CHECK-ENC: encoding: [0x93,0x82,0x03,0x19]
qc.e.addi x5, x7, 400

# CHECK-ALIAS: andi t0, t2, 750
# CHECK-NOALIAS: andi t0, t2, 750
# CHECK-ENC: encoding: [0x93,0xf2,0xe3,0x2e]
qc.e.andi x5, x7, 750

# CHECK-ALIAS: ori t0, t2, 854
# CHECK-NOALIAS: ori t0, t2, 854
# CHECK-ENC: encoding: [0x93,0xe2,0x63,0x35]
qc.e.ori x5, x7, 854

# CHECK-ALIAS: xori t0, t2, -200
# CHECK-NOALIAS: xori t0, t2, -200
# CHECK-ENC: encoding: [0x93,0xc2,0x83,0xf3]
qc.e.xori x5, x7, -200

# CHECK-ALIAS: addi t2, t2, 400
# CHECK-NOALIAS: addi t2, t2, 400
# CHECK-ENC: encoding: [0x93,0x83,0x03,0x19]
qc.e.addai x7, 400

# CHECK-ALIAS: andi t2, t2, 750
# CHECK-NOALIAS: andi t2, t2, 750
# CHECK-ENC: encoding: [0x93,0xf3,0xe3,0x2e]
qc.e.andai x7, 750

# CHECK-ALIAS: ori t2, t2, 854
# CHECK-NOALIAS: ori t2, t2, 854
# CHECK-ENC: encoding: [0x93,0xe3,0x63,0x35]
qc.e.orai x7, 854

# CHECK-ALIAS: xori t2, t2, -200
# CHECK-NOALIAS: xori t2, t2, -200
# CHECK-ENC: encoding: [0x93,0xc3,0x83,0xf3]
qc.e.xorai x7, -200
10 changes: 3 additions & 7 deletions llvm/utils/TableGen/CompressInstEmitter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -171,10 +171,6 @@ bool CompressInstEmitter::validateTypes(const Record *DagOpType,
bool IsSourceInst) {
if (DagOpType == InstOpType)
return true;
// Only source instruction operands are allowed to not match Input Dag
// operands.
if (!IsSourceInst)
return false;

if (DagOpType->isSubClassOf("RegisterClass") &&
InstOpType->isSubClassOf("RegisterClass")) {
Expand Down Expand Up @@ -258,9 +254,9 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec,
continue;
}
// Validate that Dag operand type matches the type defined in the
// corresponding instruction. Operands in the input Dag pattern are
// allowed to be a subclass of the type specified in corresponding
// instruction operand instead of being an exact match.
// corresponding instruction. Operands in the input and output Dag
// patterns are allowed to be a subclass of the type specified in the
// corresponding instruction operand instead of being an exact match.
if (!validateTypes(DI->getDef(), OpndRec, IsSourceInst))
PrintFatalError(Rec->getLoc(),
"Error in Dag '" + Dag->getAsString() +
Expand Down
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