Skip to content

Hexagon: Add frexp intrinsic test #148671

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Merged
merged 1 commit into from
Jul 15, 2025
Merged

Hexagon: Add frexp intrinsic test #148671

merged 1 commit into from
Jul 15, 2025

Conversation

@arsenm
Copy link
Contributor

@arsenm arsenm commented Jul 14, 2025

No description provided.

@arsenm arsenm marked this pull request as ready for review July 14, 2025 16:54
@arsenm Graphite App
Copy link
Contributor Author

arsenm commented Jul 14, 2025 •
edited
Loading

This stack of pull requests is managed by Graphite. Learn more about stacking.

@arsenm arsenm mentioned this pull request Jul 14, 2025
Merged
@llvmbot
Copy link
Member

llvmbot commented Jul 14, 2025

@llvm/pr-subscribers-backend-hexagon

Author: Matt Arsenault (arsenm)

Changes

Patch is 26.07 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/148671.diff

1 Files Affected:

  • (added) llvm/test/CodeGen/Hexagon/llvm.frexp.ll (+803)
diff --git a/llvm/test/CodeGen/Hexagon/llvm.frexp.ll b/llvm/test/CodeGen/Hexagon/llvm.frexp.ll
new file mode 100644
index 0000000000000..0b52e051cf251
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/llvm.frexp.ll
@@ -0,0 +1,803 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=hexagon < %s | FileCheck %s
+; RUN: llc -mtriple=hexagon-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -mtriple=hexagon-unknown-linux-musl < %s | FileCheck %s
+
+define { half, i32 } @test_frexp_f16_i32(half %a) nounwind {
+; CHECK-LABEL: test_frexp_f16_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __extendhfsf2
+; CHECK-NEXT:     allocframe(r29,#8):raw
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#4)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __truncsfhf2
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memw(r29+#4)
+; CHECK-NEXT:     dealloc_return
+; CHECK-NEXT:    }
+  %result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
+  ret { half, i32 } %result
+}
+
+define half @test_frexp_f16_i32_only_use_fract(half %a) nounwind {
+; CHECK-LABEL: test_frexp_f16_i32_only_use_fract:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __extendhfsf2
+; CHECK-NEXT:     allocframe(r29,#8):raw
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#4)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __truncsfhf2
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r31:30 = dealloc_return(r30):raw
+; CHECK-NEXT:    }
+  %result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
+  %result.0 = extractvalue { half, i32 } %result, 0
+  ret half %result.0
+}
+
+define i32 @test_frexp_f16_i32_only_use_exp(half %a) nounwind {
+; CHECK-LABEL: test_frexp_f16_i32_only_use_exp:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __extendhfsf2
+; CHECK-NEXT:     allocframe(r29,#8):raw
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#4)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = memw(r29+#4)
+; CHECK-NEXT:     dealloc_return
+; CHECK-NEXT:    }
+  %result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
+  %result.0 = extractvalue { half, i32 } %result, 1
+  ret i32 %result.0
+}
+
+define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) nounwind {
+; CHECK-LABEL: test_frexp_v2f16_v2i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r17:16 = combine(r2,r0)
+; CHECK-NEXT:     r0 = r3
+; CHECK-NEXT:     memd(r29+#-16) = r17:16
+; CHECK-NEXT:     allocframe(#32)
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __extendhfsf2
+; CHECK-NEXT:     memd(r29+#16) = r19:18
+; CHECK-NEXT:     memd(r29+#8) = r21:20
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __extendhfsf2
+; CHECK-NEXT:     r18 = r0
+; CHECK-NEXT:     r0 = r17
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#4)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __truncsfhf2
+; CHECK-NEXT:     r20 = memw(r29+#4)
+; CHECK-NEXT:     r21 = memw(r29+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __truncsfhf2
+; CHECK-NEXT:     r17 = r0
+; CHECK-NEXT:     r0 = r18
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     memh(r16+#2) = r0
+; CHECK-NEXT:     memh(r16+#0) = r17
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     memd(r16+#8) = r21:20
+; CHECK-NEXT:     r17:16 = memd(r29+#24)
+; CHECK-EMPTY:
+; CHECK-NEXT:    } :mem_noshuf // 8-byte Folded Reload
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r19:18 = memd(r29+#16)
+; CHECK-NEXT:     r21:20 = memd(r29+#8)
+; CHECK-NEXT:    } // 8-byte Folded Reload
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r31:30 = dealloc_return(r30):raw
+; CHECK-NEXT:    }
+  %result = call { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half> %a)
+  ret { <2 x half>, <2 x i32> } %result
+}
+
+define <2 x half> @test_frexp_v2f16_v2i32_only_use_fract(<2 x half> %a) nounwind {
+; CHECK-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __extendhfsf2
+; CHECK-NEXT:     r16 = r1
+; CHECK-NEXT:     memd(r29+#-16) = r17:16
+; CHECK-NEXT:     allocframe(#16)
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#4)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __truncsfhf2
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __extendhfsf2
+; CHECK-NEXT:     r17 = r0
+; CHECK-NEXT:     r0 = r16
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __truncsfhf2
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = zxth(r0)
+; CHECK-NEXT:     r2 = zxth(r17)
+; CHECK-NEXT:     r17:16 = memd(r29+#8)
+; CHECK-NEXT:    } // 8-byte Folded Reload
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = r2
+; CHECK-NEXT:     dealloc_return
+; CHECK-NEXT:    }
+  %result = call { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half> %a)
+  %result.0 = extractvalue { <2 x half>, <2 x i32> } %result, 0
+  ret <2 x half> %result.0
+}
+
+define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) nounwind {
+; CHECK-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __extendhfsf2
+; CHECK-NEXT:     r16 = r1
+; CHECK-NEXT:     memd(r29+#-16) = r17:16
+; CHECK-NEXT:     allocframe(#16)
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#4)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __extendhfsf2
+; CHECK-NEXT:     r0 = r16
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = memw(r29+#4)
+; CHECK-NEXT:     r17:16 = memd(r29+#8)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memw(r29+#0)
+; CHECK-NEXT:     dealloc_return
+; CHECK-NEXT:    }
+  %result = call { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half> %a)
+  %result.1 = extractvalue { <2 x half>, <2 x i32> } %result, 1
+  ret <2 x i32> %result.1
+}
+
+define { <3 x float>, <3 x i32> } @test_frexp_v3f32_v3i32(<3 x float> %a) nounwind {
+; CHECK-LABEL: test_frexp_v3f32_v3i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r17:16 = combine(r4,r0)
+; CHECK-NEXT:     r0 = r2
+; CHECK-NEXT:     memd(r29+#-16) = r17:16
+; CHECK-NEXT:     allocframe(#32)
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = add(r29,#4)
+; CHECK-NEXT:     r18 = r3
+; CHECK-NEXT:     memd(r29+#16) = r19:18
+; CHECK-NEXT:     memd(r29+#8) = r21:20
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r0 = r18
+; CHECK-NEXT:     r1 = add(r29,#0)
+; CHECK-NEXT:     r20 = r0
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r16,#24)
+; CHECK-NEXT:     r21 = r0
+; CHECK-NEXT:     r0 = r17
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r2 = memw(r29+#4)
+; CHECK-NEXT:     r3 = memw(r29+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     memd(r16+#0) = r21:20
+; CHECK-NEXT:     memd(r16+#16) = r3:2
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     memw(r16+#8) = r0
+; CHECK-NEXT:     r17:16 = memd(r29+#24)
+; CHECK-EMPTY:
+; CHECK-NEXT:    } :mem_noshuf // 8-byte Folded Reload
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r19:18 = memd(r29+#16)
+; CHECK-NEXT:     r21:20 = memd(r29+#8)
+; CHECK-NEXT:    } // 8-byte Folded Reload
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r31:30 = dealloc_return(r30):raw
+; CHECK-NEXT:    }
+  %result = call { <3 x float>, <3 x i32> } @llvm.frexp.v3f32.v3i32(<3 x float> %a)
+  ret { <3 x float>, <3 x i32> } %result
+}
+
+define { float, i32 } @test_frexp_f32_i32(float %a) nounwind {
+; CHECK-LABEL: test_frexp_f32_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     allocframe(r29,#8):raw
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#4)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memw(r29+#4)
+; CHECK-NEXT:     dealloc_return
+; CHECK-NEXT:    }
+  %result = call { float, i32 } @llvm.frexp.f32.i32(float %a)
+  ret { float, i32 } %result
+}
+
+define { float, i32 } @test_frexp_f32_i32_tailcall(float %a) nounwind {
+; CHECK-LABEL: test_frexp_f32_i32_tailcall:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     allocframe(r29,#8):raw
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#4)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memw(r29+#4)
+; CHECK-NEXT:     dealloc_return
+; CHECK-NEXT:    }
+  %result = tail call { float, i32 } @llvm.frexp.f32.i32(float %a)
+  ret { float, i32 } %result
+}
+
+define float @test_frexp_f32_i32_only_use_fract(float %a) nounwind {
+; CHECK-LABEL: test_frexp_f32_i32_only_use_fract:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     allocframe(r29,#8):raw
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#4)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r31:30 = dealloc_return(r30):raw
+; CHECK-NEXT:    }
+  %result = call { float, i32 } @llvm.frexp.f32.i32(float %a)
+  %result.0 = extractvalue { float, i32 } %result, 0
+  ret float %result.0
+}
+
+define i32 @test_frexp_f32_i32_only_use_exp(float %a) nounwind {
+; CHECK-LABEL: test_frexp_f32_i32_only_use_exp:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     allocframe(r29,#8):raw
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#4)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = memw(r29+#4)
+; CHECK-NEXT:     dealloc_return
+; CHECK-NEXT:    }
+  %result = call { float, i32 } @llvm.frexp.f32.i32(float %a)
+  %result.0 = extractvalue { float, i32 } %result, 1
+  ret i32 %result.0
+}
+
+define { <2 x float>, <2 x i32> } @test_frexp_v2f32_v2i32(<2 x float> %a) nounwind {
+; CHECK-LABEL: test_frexp_v2f32_v2i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r17:16 = combine(r3,r0)
+; CHECK-NEXT:     r0 = r2
+; CHECK-NEXT:     memd(r29+#-16) = r17:16
+; CHECK-NEXT:     allocframe(#24)
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#4)
+; CHECK-NEXT:     memd(r29+#8) = r19:18
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r0 = r17
+; CHECK-NEXT:     r1 = add(r29,#0)
+; CHECK-NEXT:     r18 = r0
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1:0 = combine(r0,r18)
+; CHECK-NEXT:     r2 = memw(r29+#4)
+; CHECK-NEXT:     r3 = memw(r29+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     memd(r16+#0) = r1:0
+; CHECK-NEXT:     memd(r16+#8) = r3:2
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r17:16 = memd(r29+#16)
+; CHECK-NEXT:     r19:18 = memd(r29+#8)
+; CHECK-NEXT:    } // 8-byte Folded Reload
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r31:30 = dealloc_return(r30):raw
+; CHECK-NEXT:    }
+  %result = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %a)
+  ret { <2 x float>, <2 x i32> } %result
+}
+
+define <2 x float> @test_frexp_v2f32_v2i32_only_use_fract(<2 x float> %a) nounwind {
+; CHECK-LABEL: test_frexp_v2f32_v2i32_only_use_fract:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r16 = r1
+; CHECK-NEXT:     memd(r29+#-16) = r17:16
+; CHECK-NEXT:     allocframe(#16)
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#4)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r0 = r16
+; CHECK-NEXT:     r1 = add(r29,#0)
+; CHECK-NEXT:     r17 = r0
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1:0 = combine(r0,r17)
+; CHECK-NEXT:     r17:16 = memd(r29+#8)
+; CHECK-NEXT:     dealloc_return
+; CHECK-NEXT:    } // 8-byte Folded Reload
+  %result = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %a)
+  %result.0 = extractvalue { <2 x float>, <2 x i32> } %result, 0
+  ret <2 x float> %result.0
+}
+
+define <2 x i32> @test_frexp_v2f32_v2i32_only_use_exp(<2 x float> %a) nounwind {
+; CHECK-LABEL: test_frexp_v2f32_v2i32_only_use_exp:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r16 = r1
+; CHECK-NEXT:     memd(r29+#-16) = r17:16
+; CHECK-NEXT:     allocframe(#16)
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#4)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#0)
+; CHECK-NEXT:     r0 = r16
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = memw(r29+#4)
+; CHECK-NEXT:     r17:16 = memd(r29+#8)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memw(r29+#0)
+; CHECK-NEXT:     dealloc_return
+; CHECK-NEXT:    }
+  %result = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %a)
+  %result.1 = extractvalue { <2 x float>, <2 x i32> } %result, 1
+  ret <2 x i32> %result.1
+}
+
+define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwind {
+; CHECK-LABEL: test_frexp_v4f32_v4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r17:16 = combine(r5,r0)
+; CHECK-NEXT:     r0 = r2
+; CHECK-NEXT:     memd(r29+#-16) = r17:16
+; CHECK-NEXT:     allocframe(#48)
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = add(r29,#12)
+; CHECK-NEXT:     r19:18 = combine(r3,r4)
+; CHECK-NEXT:     memd(r29+#32) = r19:18
+; CHECK-NEXT:     memd(r29+#24) = r21:20
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     memd(r29+#16) = r23:22
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r0 = r19
+; CHECK-NEXT:     r1 = add(r29,#8)
+; CHECK-NEXT:     r20 = r0
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = r18
+; CHECK-NEXT:     r1 = add(r29,#4)
+; CHECK-NEXT:     r19 = r0
+; CHECK-NEXT:     r22 = memw(r29+#12)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r23 = memw(r29+#8)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r0 = r17
+; CHECK-NEXT:     r1 = add(r29,#0)
+; CHECK-NEXT:     r18 = r0
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1:0 = combine(r0,r18)
+; CHECK-NEXT:     r5:4 = combine(r19,r20)
+; CHECK-NEXT:     r2 = memw(r29+#4)
+; CHECK-NEXT:     r3 = memw(r29+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     memd(r16+#8) = r1:0
+; CHECK-NEXT:     memd(r16+#0) = r5:4
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     memd(r16+#24) = r3:2
+; CHECK-NEXT:     memd(r16+#16) = r23:22
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r17:16 = memd(r29+#40)
+; CHECK-NEXT:     r19:18 = memd(r29+#32)
+; CHECK-NEXT:    } // 8-byte Folded Reload
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r21:20 = memd(r29+#24)
+; CHECK-NEXT:     r23:22 = memd(r29+#16)
+; CHECK-NEXT:    } // 8-byte Folded Reload
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r31:30 = dealloc_return(r30):raw
+; CHECK-NEXT:    }
+  %result = call { <4 x float>, <4 x i32> } @llvm.frexp.v4f32.v4i32(<4 x float> %a)
+  ret { <4 x float>, <4 x i32> } %result
+}
+
+define <4 x float> @test_frexp_v4f32_v4i32_only_use_fract(<4 x float> %a) nounwind {
+; CHECK-LABEL: test_frexp_v4f32_v4i32_only_use_fract:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r17:16 = combine(r5,r0)
+; CHECK-NEXT:     r0 = r2
+; CHECK-NEXT:     memd(r29+#-16) = r17:16
+; CHECK-NEXT:     allocframe(#40)
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = add(r29,#12)
+; CHECK-NEXT:     r19:18 = combine(r3,r4)
+; CHECK-NEXT:     memd(r29+#24) = r19:18
+; CHECK-NEXT:     memd(r29+#16) = r21:20
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r0 = r19
+; CHECK-NEXT:     r1 = add(r29,#8)
+; CHECK-NEXT:     r20 = r0
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r0 = r18
+; CHECK-NEXT:     r1 = add(r29,#4)
+; CHECK-NEXT:     r19 = r0
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r0 = r17
+; CHECK-NEXT:     r1 = add(r29,#0)
+; CHECK-NEXT:     r18 = r0
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1:0 = combine(r0,r18)
+; CHECK-NEXT:     r3:2 = combine(r19,r20)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     memd(r16+#8) = r1:0
+; CHECK-NEXT:     memd(r16+#0) = r3:2
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r17:16 = memd(r29+#32)
+; CHECK-NEXT:     r19:18 = memd(r29+#24)
+; CHECK-NEXT:    } // 8-byte Folded Reload
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r21:20 = memd(r29+#16)
+; CHECK-NEXT:     dealloc_return
+; CHECK-NEXT:    } // 8-byte Folded Reload
+  %result = call { <4 x float>, <4 x i32> } @llvm.frexp.v4f32.v4i32(<4 x float> %a)
+  %result.0 = extractvalue { <4 x float>, <4 x i32> } %result, 0
+  ret <4 x float> %result.0
+}
+
+define <4 x i32> @test_frexp_v4f32_v4i32_only_use_exp(<4 x float> %a) nounwind {
+; CHECK-LABEL: test_frexp_v4f32_v4i32_only_use_exp:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r17:16 = combine(r5,r0)
+; CHECK-NEXT:     r0 = r2
+; CHECK-NEXT:     memd(r29+#-16) = r17:16
+; CHECK-NEXT:     allocframe(#32)
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r19:18 = combine(r3,r4)
+; CHECK-NEXT:     r1 = add(r29,#12)
+; CHECK-NEXT:     memd(r29+#16) = r19:18
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#8)
+; CHECK-NEXT:     r0 = r19
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#4)
+; CHECK-NEXT:     r0 = r18
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexpf
+; CHECK-NEXT:     r1 = add(r29,#0)
+; CHECK-NEXT:     r0 = r17
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = memw(r29+#12)
+; CHECK-NEXT:     r2 = memw(r29+#4)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memw(r29+#8)
+; CHECK-NEXT:     r3 = memw(r29+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     memd(r16+#8) = r3:2
+; CHECK-NEXT:     memd(r16+#0) = r1:0
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r17:16 = memd(r29+#24)
+; CHECK-NEXT:     r19:18 = memd(r29+#16)
+; CHECK-NEXT:    } // 8-byte Folded Reload
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r31:30 = dealloc_return(r30):raw
+; CHECK-NEXT:    }
+  %result = call { <4 x float>, <4 x i32> } @llvm.frexp.v4f32.v4i32(<4 x float> %a)
+  %result.1 = extractvalue { <4 x float>, <4 x i32> } %result, 1
+  ret <4 x i32> %result.1
+}
+
+define { double, i32 } @test_frexp_f64_i32(double %a) nounwind {
+; CHECK-LABEL: test_frexp_f64_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r16 = r0
+; CHECK-NEXT:     r1:0 = combine(r3,r2)
+; CHECK-NEXT:     memd(r29+#-16) = r17:16
+; CHECK-NEXT:     allocframe(#8)
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call frexp
+; CHECK-NEXT:     r2 = add(r16,#8)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     memd(r16+#0) = r1:0
+; CHECK-NEXT:     r17:16 = memd(r29+#0)
+; CHECK-EMPTY:
+...
[truncated]

aankit-ca
aankit-ca reviewed Jul 14, 2025
View reviewed changes
Copy link
Contributor

@aankit-ca aankit-ca left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM

@arsenm Graphite App
Copy link
Contributor Author

arsenm commented Jul 14, 2025 •
edited
Loading

Merge activity

  • Jul 14, 11:46 PM UTC: A user started a stack merge that includes this pull request via Graphite.
  • Jul 14, 11:57 PM UTC: Graphite rebased this pull request as part of a merge.
  • Jul 15, 12:00 AM UTC: @arsenm merged this pull request with Graphite.

@arsenm arsenm force-pushed the users/arsenm/hexagon/add-exp10-intrinsic-test branch 3 times, most recently from 979c7e2 to fb800e1 Compare July 14, 2025 23:54
Base automatically changed from users/arsenm/hexagon/add-exp10-intrinsic-test to main July 14, 2025 23:56
@arsenm arsenm force-pushed the users/arsenm/hexagon/add-frexp-intrinsic-test branch from b77581c to 4465732 Compare July 14, 2025 23:56
@arsenm arsenm merged commit ee5b936 into main Jul 15, 2025
7 of 9 checks passed
@arsenm arsenm deleted the users/arsenm/hexagon/add-frexp-intrinsic-test branch July 15, 2025 00:00
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

@aankit-ca aankit-ca aankit-ca left review comments

Assignees

No one assigned

Labels

backend:Hexagon

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

4 participants

@arsenm @llvmbot @aankit-ca