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[RISCV] Render P-ext simm10_unsigned as a simm10 after parsing. #148749

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Merged
merged 2 commits into from
Jul 15, 2025
Merged

[RISCV] Render P-ext simm10_unsigned as a simm10 after parsing. #148749

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f6b643e
[RISCV] Render P-ext simm10_unsigned as a simm10 after parsing.
topperc Jul 14, 2025
df20d29
fixup! Address review comment
topperc Jul 15, 2025
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8 changes: 8 additions & 0 deletions llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1199,6 +1199,14 @@ struct RISCVOperand final : public MCParsedAsmOperand {
addExpr(Inst, getImm(), isRV64Imm());
}

void addSImm10UnsignedOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
int64_t Imm;
[[maybe_unused]] bool IsConstant = evaluateConstantImm(getImm(), Imm);
assert(IsConstant);
Inst.addOperand(MCOperand::createImm(SignExtend64<10>(Imm)));
}

void addFPImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
if (isImm()) {
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1 change: 0 additions & 1 deletion llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
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Expand Up @@ -339,7 +339,6 @@ enum OperandType : unsigned {
OPERAND_SIMM6,
OPERAND_SIMM6_NONZERO,
OPERAND_SIMM10,
OPERAND_SIMM10_UNSIGNED,
OPERAND_SIMM10_LSB0000_NONZERO,
OPERAND_SIMM11,
OPERAND_SIMM12,
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10 changes: 7 additions & 3 deletions llvm/lib/Target/RISCV/RISCVInstrInfoP.td
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Expand Up @@ -20,18 +20,22 @@

def simm10 : RISCVSImmLeafOp<10>;

def SImm10UnsignedAsmOperand : SImmAsmOperand<10, "Unsigned"> {
let RenderMethod = "addSImm10UnsignedOperands";
}

// A 10-bit signed immediate allowing range [-512, 1023]
// but will decode to [-512, 511].
def simm10_unsigned : RISCVOp {
let ParserMatchClass = SImmAsmOperand<10, "Unsigned">;
let ParserMatchClass = SImm10UnsignedAsmOperand;
let EncoderMethod = "getImmOpValue";
let DecoderMethod = "decodeSImmOperand<10>";
let OperandType = "OPERAND_SIMM10_UNSIGNED";
let OperandType = "OPERAND_SIMM10";
let MCOperandPredicate = [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
return isInt<10>(Imm) || isUInt<10>(Imm);
return isInt<10>(Imm);
}];
}

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5 changes: 2 additions & 3 deletions llvm/test/MC/RISCV/rv32p-valid.s
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Expand Up @@ -2,7 +2,7 @@
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-p < %s \
# RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r --no-print-imm-hex - \
# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ,CHECK-OBJ %s
# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s

# CHECK-ASM-AND-OBJ: clz a0, a1
# CHECK-ASM: encoding: [0x13,0x95,0x05,0x60]
Expand Down Expand Up @@ -73,7 +73,6 @@ psabs.b t0, t1
# CHECK-ASM-AND-OBJ: plui.h gp, 32
# CHECK-ASM: encoding: [0x9b,0x21,0x20,0xf0]
plui.h gp, 32
# CHECK-OBJ: plui.h gp, -412
# CHECK-ASM: plui.h gp, 612
# CHECK-ASM-AND-OBJ: plui.h gp, -412
# CHECK-ASM: encoding: [0x9b,0xa1,0x64,0xf0]
plui.h gp, 612
8 changes: 3 additions & 5 deletions llvm/test/MC/RISCV/rv64p-valid.s
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Expand Up @@ -2,7 +2,7 @@
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj --triple=riscv64 -mattr=+experimental-p < %s \
# RUN: | llvm-objdump --triple=riscv64 --mattr=+experimental-p -M no-aliases --no-print-imm-hex -d -r - \
# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ,CHECK-OBJ %s
# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s

# CHECK-ASM-AND-OBJ: clz a0, a1
# CHECK-ASM: encoding: [0x13,0x95,0x05,0x60]
Expand Down Expand Up @@ -97,14 +97,12 @@ psabs.b a0, s2
# CHECK-ASM-AND-OBJ: plui.h s2, 4
# CHECK-ASM: encoding: [0x1b,0x29,0x04,0xf0]
plui.h s2, 4
# CHECK-OBJ: plui.h gp, -412
# CHECK-ASM: plui.h gp, 612
# CHECK-ASM-AND-OBJ: plui.h gp, -412
# CHECK-ASM: encoding: [0x9b,0xa1,0x64,0xf0]
plui.h gp, 612
# CHECK-ASM-AND-OBJ: plui.w a2, 1
# CHECK-ASM: encoding: [0x1b,0x26,0x01,0xf2]
plui.w a2, 1
# CHECK-OBJ: plui.w a2, -1
# CHECK-ASM: plui.w a2, 1023
# CHECK-ASM-AND-OBJ: plui.w a2, -1
# CHECK-ASM: encoding: [0x1b,0xa6,0xff,0xf3]
plui.w a2, 1023
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