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[AArch64] Add zero cycle register move statistics #149033

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[AArch64] Add zero cycle register move statistics #149033

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50 changes: 48 additions & 2 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/CFIInstBuilder.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
Expand Down Expand Up @@ -60,9 +61,22 @@

using namespace llvm;

#define DEBUG_TYPE "aarch64-instr-info"

#define GET_INSTRINFO_CTOR_DTOR
#include "AArch64GenInstrInfo.inc"

STATISTIC(NumZeroCycleRegMoveGPR32,
"Number of lowered zero cycle register moves of GPR32 class");
STATISTIC(NumZeroCycleRegMoveGPR64,
"Number of lowered zero cycle register moves of GPR64 class");
STATISTIC(NumZeroCycleRegMoveFPR128,
"Number of lowered zero cycle register moves of FPR128 class");
STATISTIC(NumZeroCycleRegMoveFPR64,
"Number of lowered zero cycle register moves of FPR64 class");
STATISTIC(NumZeroCycleRegMoveFPR32,
"Number of lowered zero cycle register moves of FPR32 class");

static cl::opt<unsigned>
CBDisplacementBits("aarch64-cb-offset-bits", cl::Hidden, cl::init(9),
cl::desc("Restrict range of CB instructions (DEBUG)"));
Expand Down Expand Up @@ -5061,11 +5075,15 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addImm(0)
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
++NumZeroCycleRegMoveGPR64;
} else {
BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc))
.addImm(0)
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
if (Subtarget.hasZeroCycleRegMoveGPR32()) {
++NumZeroCycleRegMoveGPR32;
}
}
} else if (SrcReg == AArch64::WZR && Subtarget.hasZeroCycleZeroingGP()) {
BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg)
Expand All @@ -5087,11 +5105,15 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(AArch64::XZR)
.addReg(SrcRegX, RegState::Undef)
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
++NumZeroCycleRegMoveGPR64;
} else {
// Otherwise, expand to ORR WZR.
BuildMI(MBB, I, DL, get(AArch64::ORRWrr), DestReg)
.addReg(AArch64::WZR)
.addReg(SrcReg, getKillRegState(KillSrc));
if (Subtarget.hasZeroCycleRegMoveGPR32()) {
++NumZeroCycleRegMoveGPR32;
}
}
}
return;
Expand Down Expand Up @@ -5189,6 +5211,9 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(SrcReg, getKillRegState(KillSrc))
.addImm(0)
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
if (Subtarget.hasZeroCycleRegMoveGPR64()) {
++NumZeroCycleRegMoveGPR64;
}
} else if (SrcReg == AArch64::XZR && Subtarget.hasZeroCycleZeroingGP()) {
BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg)
.addImm(0)
Expand All @@ -5198,6 +5223,9 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg)
.addReg(AArch64::XZR)
.addReg(SrcReg, getKillRegState(KillSrc));
if (Subtarget.hasZeroCycleRegMoveGPR64()) {
++NumZeroCycleRegMoveGPR64;
}
}
return;
}
Expand Down Expand Up @@ -5284,11 +5312,14 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(AArch64::Z0 + (DestReg - AArch64::Q0), RegState::Define)
.addReg(AArch64::Z0 + (SrcReg - AArch64::Q0))
.addReg(AArch64::Z0 + (SrcReg - AArch64::Q0));
else if (Subtarget.isNeonAvailable())
else if (Subtarget.isNeonAvailable()) {
BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
.addReg(SrcReg)
.addReg(SrcReg, getKillRegState(KillSrc));
else {
// if (Subtarget.hasZeroCycleRegMoveFPR128()) { need rebase
++NumZeroCycleRegMoveFPR128;
// }
} else {
BuildMI(MBB, I, DL, get(AArch64::STRQpre))
.addReg(AArch64::SP, RegState::Define)
.addReg(SrcReg, getKillRegState(KillSrc))
Expand All @@ -5307,6 +5338,9 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
AArch64::FPR64RegClass.contains(SrcReg)) {
BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
if (Subtarget.hasZeroCycleRegMoveFPR64()) {
++NumZeroCycleRegMoveFPR64;
}
return;
}

Expand All @@ -5326,9 +5360,13 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestRegD)
.addReg(SrcRegD, RegState::Undef)
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
++NumZeroCycleRegMoveFPR64;
} else {
BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
if (Subtarget.hasZeroCycleRegMoveFPR32()) {
++NumZeroCycleRegMoveFPR32;
}
}
return;
}
Expand All @@ -5349,13 +5387,17 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestRegD)
.addReg(SrcRegD, RegState::Undef)
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
++NumZeroCycleRegMoveFPR64;
} else {
DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
&AArch64::FPR32RegClass);
SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
&AArch64::FPR32RegClass);
BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
if (Subtarget.hasZeroCycleRegMoveFPR32()) {
++NumZeroCycleRegMoveFPR32;
}
}
return;
}
Expand All @@ -5376,13 +5418,17 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestRegD)
.addReg(SrcRegD, RegState::Undef)
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
++NumZeroCycleRegMoveFPR64;
} else {
DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
&AArch64::FPR32RegClass);
SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
&AArch64::FPR32RegClass);
BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
if (Subtarget.hasZeroCycleRegMoveFPR32()) {
++NumZeroCycleRegMoveFPR32;
}
}
return;
}
Expand Down
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