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[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes #149071

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Merged
merged 4 commits into from
Jul 20, 2025
Merged

[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes #149071

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13ae58a
[RISCV][NFC] Add NumTransformedToNonWInstrs statistic to RISCVOptWIns…
asb Jul 16, 2025
86b1b14
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes
asb Jul 16, 2025
be46fed
Merge remote-tracking branch 'origin/main' into 2025q3-riscv-stripwsu…
asb Jul 20, 2025
e3bae5b
Merge remote-tracking branch 'origin/main' into 2025q3-riscv-stripwsu…
asb Jul 20, 2025
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8 changes: 8 additions & 0 deletions llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,8 @@ using namespace llvm;
STATISTIC(NumRemovedSExtW, "Number of removed sign-extensions");
STATISTIC(NumTransformedToWInstrs,
"Number of instructions transformed to W-ops");
STATISTIC(NumTransformedToNonWInstrs,
"Number of instructions transformed to non-W-ops");

static cl::opt<bool> DisableSExtWRemoval("riscv-disable-sextw-removal",
cl::desc("Disable removal of sext.w"),
Expand Down Expand Up @@ -729,17 +731,23 @@ bool RISCVOptWInstrs::stripWSuffixes(MachineFunction &MF,
for (MachineBasicBlock &MBB : MF) {
for (MachineInstr &MI : MBB) {
unsigned Opc;
// clang-format off
switch (MI.getOpcode()) {
default:
continue;
case RISCV::ADDW: Opc = RISCV::ADD; break;
case RISCV::ADDIW: Opc = RISCV::ADDI; break;
case RISCV::MULW: Opc = RISCV::MUL; break;
case RISCV::SLLIW: Opc = RISCV::SLLI; break;
case RISCV::SUBW: Opc = RISCV::SUB; break;
}
// clang-format on

if (hasAllWUsers(MI, ST, MRI)) {
LLVM_DEBUG(dbgs() << "Replacing " << MI);
MI.setDesc(TII.get(Opc));
LLVM_DEBUG(dbgs() << " with " << MI);
++NumTransformedToNonWInstrs;
MadeChange = true;
}
}
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -66,7 +66,7 @@ define i32 @udiv_constant_add(i32 %a) nounwind {
; RV64IM-NEXT: srli a2, a2, 32
; RV64IM-NEXT: mul a1, a2, a1
; RV64IM-NEXT: srli a1, a1, 32
; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: sub a0, a0, a1
; RV64IM-NEXT: srliw a0, a0, 1
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: srliw a0, a0, 2
Expand All @@ -79,7 +79,7 @@ define i32 @udiv_constant_add(i32 %a) nounwind {
; RV64IMZB-NEXT: zext.w a2, a0
; RV64IMZB-NEXT: mul a1, a2, a1
; RV64IMZB-NEXT: srli a1, a1, 32
; RV64IMZB-NEXT: subw a0, a0, a1
; RV64IMZB-NEXT: sub a0, a0, a1
; RV64IMZB-NEXT: srliw a0, a0, 1
; RV64IMZB-NEXT: add a0, a0, a1
; RV64IMZB-NEXT: srliw a0, a0, 2
Expand Down Expand Up @@ -250,7 +250,7 @@ define i8 @udiv8_constant_add(i8 %a) nounwind {
; RV64-NEXT: zext.b a2, a0
; RV64-NEXT: mul a1, a2, a1
; RV64-NEXT: srli a1, a1, 8
; RV64-NEXT: subw a0, a0, a1
; RV64-NEXT: sub a0, a0, a1
; RV64-NEXT: zext.b a0, a0
; RV64-NEXT: srli a0, a0, 1
; RV64-NEXT: add a0, a0, a1
Expand Down Expand Up @@ -816,7 +816,7 @@ define i8 @sdiv8_constant_sub_srai(i8 %a) nounwind {
; RV64IM-NEXT: mul a1, a2, a1
; RV64IM-NEXT: slli a1, a1, 48
; RV64IM-NEXT: srai a1, a1, 56
; RV64IM-NEXT: subw a1, a1, a0
; RV64IM-NEXT: sub a1, a1, a0
; RV64IM-NEXT: slli a1, a1, 56
; RV64IM-NEXT: srai a0, a1, 58
; RV64IM-NEXT: zext.b a1, a0
Expand Down Expand Up @@ -1071,7 +1071,7 @@ define i16 @sdiv16_constant_sub_srai(i16 %a) nounwind {
; RV64IM-NEXT: srai a2, a2, 48
; RV64IM-NEXT: mul a1, a2, a1
; RV64IM-NEXT: sraiw a1, a1, 16
; RV64IM-NEXT: subw a1, a1, a0
; RV64IM-NEXT: sub a1, a1, a0
; RV64IM-NEXT: slli a1, a1, 48
; RV64IM-NEXT: srai a0, a1, 51
; RV64IM-NEXT: slli a1, a0, 48
Expand Down
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