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[AMDGPU] Select flat GVS loads on gfx1250 #149183

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Merged
merged 2 commits into from
Jul 16, 2025
Merged

[AMDGPU] Select flat GVS loads on gfx1250 #149183

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a41be25
[AMDGPU] gfx1250 MC support for FLAT GVS addressing
rampitec Jul 16, 2025
64dd70f
[AMDGPU] Select flat GVS loads on gfx1250
rampitec Jul 16, 2025
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10 changes: 10 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPU.td
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Original file line number Diff line number Diff line change
Expand Up @@ -89,6 +89,12 @@ def FeatureEnableFlatScratch : SubtargetFeature<"enable-flat-scratch",
"Use scratch_* flat memory instructions to access scratch"
>;

def FeatureFlatGVSMode : SubtargetFeature<"flat-gvs-mode",
"FlatGVSMode",
"true",
"Have GVS addressing mode with flat_* instructions"
>;

def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
"AddNoCarryInsts",
"true",
Expand Down Expand Up @@ -1954,6 +1960,7 @@ def FeatureISAVersion12_50 : FeatureSet<
FeatureShaderCyclesHiLoRegisters,
FeatureArchitectedFlatScratch,
FeatureArchitectedSGPRs,
FeatureFlatGVSMode,
FeatureAtomicFaddRtnInsts,
FeatureAtomicFaddNoRtnInsts,
FeatureAtomicDsPkAdd16Insts,
Expand Down Expand Up @@ -2381,6 +2388,9 @@ def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
def HasFlatScratchSVSMode : Predicate<"Subtarget->hasFlatScratchSVSMode()">,
AssemblerPredicate<(any_of FeatureGFX940Insts, FeatureGFX11Insts)>;

def HasFlatGVSMode : Predicate<"Subtarget->hasFlatGVSMode()">,
AssemblerPredicate<(all_of FeatureFlatGVSMode)>;

def HasGFX10_AEncoding : Predicate<"Subtarget->hasGFX10_AEncoding()">,
AssemblerPredicate<(all_of FeatureGFX10_AEncoding)>;

Expand Down
406 changes: 247 additions & 159 deletions llvm/lib/Target/AMDGPU/FLATInstructions.td
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3 changes: 3 additions & 0 deletions llvm/lib/Target/AMDGPU/GCNSubtarget.h
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Original file line number Diff line number Diff line change
Expand Up @@ -214,6 +214,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool FlatInstOffsets = false;
bool FlatGlobalInsts = false;
bool FlatScratchInsts = false;
bool FlatGVSMode = false;
bool ScalarFlatScratchInsts = false;
bool HasArchitectedFlatScratch = false;
bool EnableFlatScratch = false;
Expand Down Expand Up @@ -1160,6 +1161,8 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,

bool hasLshlAddU64Inst() const { return HasLshlAddU64Inst; }

bool hasFlatGVSMode() const { return FlatGVSMode; }

bool enableSIScheduler() const {
return EnableSIScheduler;
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Expand Up @@ -6460,7 +6460,7 @@ bool SIInstrInfo::moveFlatAddrToVGPR(MachineInstr &Inst) const {
if (OldSAddrIdx < 0)
return false;

assert(isSegmentSpecificFLAT(Inst));
assert(isSegmentSpecificFLAT(Inst) || (isFLAT(Inst) && ST.hasFlatGVSMode()));

int NewOpc = AMDGPU::getGlobalVaddrOp(Opc);
if (NewOpc < 0)
Expand Down Expand Up @@ -6537,7 +6537,7 @@ bool SIInstrInfo::moveFlatAddrToVGPR(MachineInstr &Inst) const {
// FIXME: Remove this when SelectionDAG is obsoleted.
void SIInstrInfo::legalizeOperandsFLAT(MachineRegisterInfo &MRI,
MachineInstr &MI) const {
if (!isSegmentSpecificFLAT(MI))
if (!isSegmentSpecificFLAT(MI) && !ST.hasFlatGVSMode())
return;

// Fixup SGPR operands in VGPRs. We only select these when the DAG divergence
Expand Down
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