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[RISCV] Handled the uimm9 offset while FrameIndex folding. #149303

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Merged
merged 4 commits into from
Jul 30, 2025
Merged

[RISCV] Handled the uimm9 offset while FrameIndex folding. #149303

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16e7516
Handle and honour the uimm9 offset for mips prefetch.
ukalappa-mips Jul 17, 2025
e8177b2
Updated the comments and testcase updated.
ukalappa-mips Jul 18, 2025
ed463e0
Removed the redundant checks.
ukalappa-mips Jul 22, 2025
f5a314c
Updated the testcase.
ukalappa-mips Jul 22, 2025
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8 changes: 4 additions & 4 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2942,8 +2942,8 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
/// Similar to SelectAddrRegImm, except that the offset is restricted to uimm9.
bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
SDValue &Offset) {
// FIXME: Support FrameIndex. Need to teach eliminateFrameIndex that only
// a 9-bit immediate can be folded.
if (SelectAddrFrameIndex(Addr, Base, Offset))
return true;

SDLoc DL(Addr);
MVT VT = Addr.getSimpleValueType();
Expand All @@ -2953,8 +2953,8 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
if (isUInt<9>(CVal)) {
Base = Addr.getOperand(0);

// FIXME: Support FrameIndex. Need to teach eliminateFrameIndex that only
// a 9-bit immediate can be folded.
if (auto *FIN = dyn_cast<FrameIndexSDNode>(Base))
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), VT);
Offset = CurDAG->getSignedTargetConstant(CVal, DL, VT);
return true;
}
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5 changes: 5 additions & 0 deletions llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
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Expand Up @@ -573,6 +573,8 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int64_t Val = Offset.getFixed();
int64_t Lo12 = SignExtend64<12>(Val);
unsigned Opc = MI.getOpcode();
auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();

if (Opc == RISCV::ADDI && !isInt<12>(Val)) {
// We chose to emit the canonical immediate sequence rather than folding
// the offset into the using add under the theory that doing so doesn't
Expand All @@ -585,6 +587,9 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
(Lo12 & 0b11111) != 0) {
// Prefetch instructions require the offset to be 32 byte aligned.
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
} else if (Opc == RISCV::MIPS_PREFETCH && !isUInt<9>(Val)) {
// MIPS Prefetch instructions require the offset to be 9 bits encoded.
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
} else if ((Opc == RISCV::PseudoRV32ZdinxLD ||
Opc == RISCV::PseudoRV32ZdinxSD) &&
Lo12 >= 2044) {
Expand Down
56 changes: 54 additions & 2 deletions llvm/test/CodeGen/RISCV/xmips-cbop.ll
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@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=riscv32 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv32 -mattr=+xmipscbop -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32XMIPSPREFETCH
; RUN: llc -mtriple=riscv64 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -mattr=+xmipscbop -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64XMIPSPREFETCH

define void @prefetch_data_read(ptr noundef %ptr) nounwind {
Expand Down Expand Up @@ -49,3 +49,55 @@ define void @prefetch_inst_read(ptr noundef %ptr) nounwind {
tail call void @llvm.prefetch.p0(ptr nonnull %arrayidx, i32 0, i32 0, i32 0)
ret void
}

define void @prefetch_frameindex_test_neg() nounwind {
; RV32XMIPSPREFETCH-LABEL: prefetch_frameindex_test_neg:
; RV32XMIPSPREFETCH: # %bb.0:
; RV32XMIPSPREFETCH-NEXT: lui a0, 1
; RV32XMIPSPREFETCH-NEXT: addi a0, a0, 16
; RV32XMIPSPREFETCH-NEXT: sub sp, sp, a0
; RV32XMIPSPREFETCH-NEXT: addi a0, sp, 524
; RV32XMIPSPREFETCH-NEXT: mips.pref 8, 0(a0)
; RV32XMIPSPREFETCH-NEXT: lui a0, 1
; RV32XMIPSPREFETCH-NEXT: addi a0, a0, 16
; RV32XMIPSPREFETCH-NEXT: add sp, sp, a0
; RV32XMIPSPREFETCH-NEXT: ret
;
; RV64XMIPSPREFETCH-LABEL: prefetch_frameindex_test_neg:
; RV64XMIPSPREFETCH: # %bb.0:
; RV64XMIPSPREFETCH-NEXT: lui a0, 1
; RV64XMIPSPREFETCH-NEXT: addi a0, a0, 16
; RV64XMIPSPREFETCH-NEXT: sub sp, sp, a0
; RV64XMIPSPREFETCH-NEXT: addi a0, sp, 524
; RV64XMIPSPREFETCH-NEXT: mips.pref 8, 0(a0)
; RV64XMIPSPREFETCH-NEXT: lui a0, 1
; RV64XMIPSPREFETCH-NEXT: addi a0, a0, 16
; RV64XMIPSPREFETCH-NEXT: add sp, sp, a0
; RV64XMIPSPREFETCH-NEXT: ret
%data = alloca [1024 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [127 x i32], ptr %base, i32 0, i32 127
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}

define void @prefetch_frameindex_test() nounwind {
; RV32XMIPSPREFETCH-LABEL: prefetch_frameindex_test:
; RV32XMIPSPREFETCH: # %bb.0:
; RV32XMIPSPREFETCH-NEXT: addi sp, sp, -512
; RV32XMIPSPREFETCH-NEXT: mips.pref 8, 32(sp)
; RV32XMIPSPREFETCH-NEXT: addi sp, sp, 512
; RV32XMIPSPREFETCH-NEXT: ret
;
; RV64XMIPSPREFETCH-LABEL: prefetch_frameindex_test:
; RV64XMIPSPREFETCH: # %bb.0:
; RV64XMIPSPREFETCH-NEXT: addi sp, sp, -512
; RV64XMIPSPREFETCH-NEXT: mips.pref 8, 32(sp)
; RV64XMIPSPREFETCH-NEXT: addi sp, sp, 512
; RV64XMIPSPREFETCH-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 8
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
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