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[LSR] Do not consider uses in lifetime intrinsics #149492

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Merged
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Jul 18, 2025
Merged

[LSR] Do not consider uses in lifetime intrinsics #149492

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76a87fd
[LSR] Add test where liftime use is rewritten (NFC)
nikic Jul 18, 2025
29dc663
[LSR] Do not consider uses in lifetime intrinsics
nikic Jul 18, 2025
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5 changes: 5 additions & 0 deletions llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3790,6 +3790,11 @@ LSRInstance::CollectLoopInvariantFixupsAndFormulae() {
continue;
}

// Do not consider uses inside lifetime intrinsics. These are not
// actually materialized.
if (UserInst->isLifetimeStartOrEnd())
continue;

std::pair<size_t, Immediate> P =
getUse(S, LSRUse::Basic, MemAccessTy());
size_t LUIdx = P.first;
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59 changes: 59 additions & 0 deletions llvm/test/Transforms/LoopStrengthReduce/X86/lifetime-use.ll
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@@ -0,0 +1,59 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S -passes=loop-reduce -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s

define void @test(ptr %p, i64 %idx) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[P:%.*]], i64 [[IDX:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [4 x [4 x i32]], align 16
; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 64, ptr [[ALLOCA]])
; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[IDX]], 6
; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[TMP0]], 48
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP1]]
; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr nuw i8, ptr [[ALLOCA]], i64 48
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ -8, %[[ENTRY]] ]
; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i64 [[LSR_IV]], 2
; CHECK-NEXT: [[SCEVGEP8:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP2]]
; CHECK-NEXT: [[SCEVGEP9:%.*]] = getelementptr i8, ptr [[SCEVGEP8]], i64 32
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[SCEVGEP9]], align 4
; CHECK-NEXT: [[SCEVGEP6:%.*]] = getelementptr i8, ptr [[P]], i64 [[LSR_IV]]
; CHECK-NEXT: [[SCEVGEP7:%.*]] = getelementptr i8, ptr [[SCEVGEP6]], i64 8
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[SCEVGEP7]], align 4
; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i8, ptr [[SCEVGEP3]], i64 [[LSR_IV]]
; CHECK-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[SCEVGEP4]], i64 8
; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[SCEVGEP5]], align 4
; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[LSR_IV]]
; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[SCEVGEP1]], i64 8
; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[SCEVGEP2]], align 4
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], 4
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 0
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 64, ptr [[ALLOCA]])
; CHECK-NEXT: ret void
;
entry:
%alloca = alloca [4 x [4 x i32]], align 16
call void @llvm.lifetime.start.p0(i64 64, ptr %alloca)
br label %loop

loop:
%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %loop ]
%gep1 = getelementptr [4 x [12 x [4 x [4 x i32]]]], ptr %p, i64 0, i64 0, i64 0, i64 %indvars.iv, i64 0
%0 = load i32, ptr %gep1, align 4
%gep2 = getelementptr [6 x [4 x [4 x i32]]], ptr %p, i64 0, i64 0, i64 0, i64 %indvars.iv
%1 = load i32, ptr %gep2, align 4
%gep3 = getelementptr [4 x [4 x i32]], ptr %alloca, i64 0, i64 3, i64 %indvars.iv
%2 = load i32, ptr %gep3, align 4
%gep4 = getelementptr [6 x [4 x [4 x i32]]], ptr %p, i64 0, i64 %idx, i64 3, i64 %indvars.iv
%3 = load i32, ptr %gep4, align 4
%indvars.iv.next = add i64 %indvars.iv, 1
%exitcond.not = icmp eq i64 %indvars.iv, 1
br i1 %exitcond.not, label %exit, label %loop

exit:
call void @llvm.lifetime.end.p0(i64 64, ptr %alloca)
ret void
}
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