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18 changes: 17 additions & 1 deletion llvm/lib/Target/X86/X86ISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -23479,7 +23479,6 @@ static SDValue EmitCmp(SDValue Op0, SDValue Op1, X86::CondCode X86CC,
}

// Try to shrink i64 compares if the input has enough zero bits.
// TODO: Add sign-bits equivalent for isX86CCSigned(X86CC)?
if (CmpVT == MVT::i64 && !isX86CCSigned(X86CC) &&
Op0.hasOneUse() && // Hacky way to not break CSE opportunities with sub.
DAG.MaskedValueIsZero(Op1, APInt::getHighBitsSet(64, 32)) &&
Expand All @@ -23489,6 +23488,23 @@ static SDValue EmitCmp(SDValue Op0, SDValue Op1, X86::CondCode X86CC,
Op1 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op1);
}

// Try to shrink signed i64 compares if the input has enough one bits.
// Or the input is sign extended from a 32-bit value.
// TODO: Should we peek through freeze?
// TODO: Is SIGN_EXTEND_INREG needed here?
if (CmpVT == MVT::i64 && isX86CCSigned(X86CC) &&
Op0.hasOneUse() && // Hacky way to not break CSE opportunities with sub.
(DAG.MaskedValueIsAllOnes(Op1, APInt::getHighBitsSet(64, 32)) ||
Op1.getOpcode() == ISD::SIGN_EXTEND ||
Op1.getOpcode() == ISD::SIGN_EXTEND_INREG) &&
(DAG.MaskedValueIsAllOnes(Op0, APInt::getHighBitsSet(64, 32)) ||
Op0.getOpcode() == ISD::SIGN_EXTEND ||
Op0.getOpcode() == ISD::SIGN_EXTEND_INREG)) {
CmpVT = MVT::i32;
Op0 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op0);
Op1 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op1);
}

// 0-x == y --> x+y == 0
// 0-x != y --> x+y != 0
if (Op0.getOpcode() == ISD::SUB && isNullConstant(Op0.getOperand(0)) &&
Expand Down
12 changes: 12 additions & 0 deletions llvm/test/CodeGen/X86/cmp.ll
Original file line number Diff line number Diff line change
Expand Up @@ -956,3 +956,15 @@ define i1 @fold_test_and_with_chain(ptr %x, ptr %y, i32 %z) {
store i32 %z, ptr %y
ret i1 %c
}

define i1 @sext_mask(i32 %a) {
; CHECK-LABEL: sext_mask:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpl $-523, %edi # encoding: [0x81,0xff,0xf5,0xfd,0xff,0xff]
; CHECK-NEXT: # imm = 0xFDF5
; CHECK-NEXT: setl %al # encoding: [0x0f,0x9c,0xc0]
; CHECK-NEXT: retq # encoding: [0xc3]
%a64 = sext i32 %a to i64
%v1 = icmp slt i64 %a64, -523
ret i1 %v1
}
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