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[RISCV] Make RISCVVPseudo extend Pseudo. NFC #149785

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Merged
lukel97 merged 4 commits into from
Jul 23, 2025
Merged

[RISCV] Make RISCVVPseudo extend Pseudo. NFC #149785

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d9473a1
[RISCV] Copy base instruction TSFlags in RVV pseudo TSFlags. NFC
lukel97 Jul 21, 2025
7321018
Indent tablgen properly
lukel97 Jul 21, 2025
2590e74
Don't copy over TSFlags
lukel97 Jul 22, 2025
3f66dc8
Default pattern to []
lukel97 Jul 23, 2025
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249 changes: 97 additions & 152 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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6 changes: 2 additions & 4 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
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Original file line number Diff line number Diff line change
Expand Up @@ -448,11 +448,10 @@ class NDSRVInstVLN<bits<5> funct5, string opcodestr>
}

class VPseudoVLN8NoMask<VReg RetClass, bit U> :
Pseudo<(outs RetClass:$rd),
RISCVVPseudo<(outs RetClass:$rd),
(ins RetClass:$dest,
GPRMemZeroOffset:$rs1,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVNDSVLN</*Masked*/0, /*Unsigned*/U, !logtwo(8), VLMul> {
let mayLoad = 1;
let mayStore = 0;
Expand All @@ -464,11 +463,10 @@ class VPseudoVLN8NoMask<VReg RetClass, bit U> :
}

class VPseudoVLN8Mask<VReg RetClass, bit U> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMemZeroOffset:$rs1,
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVNDSVLN</*Masked*/1, /*Unsigned*/U, !logtwo(8), VLMul> {
let mayLoad = 1;
let mayStore = 0;
Expand Down
10 changes: 4 additions & 6 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
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Expand Up @@ -154,18 +154,16 @@ foreach m = MxList in {
let VLMul = m.value in {
let BaseInstr = RI_VEXTRACT in
def PseudoRI_VEXTRACT_ # mx :
Pseudo<(outs GPR:$rd), (ins m.vrclass:$rs2, uimm5:$idx, ixlenimm:$sew),
[]>,
RISCVVPseudo;
RISCVVPseudo<(outs GPR:$rd), (ins m.vrclass:$rs2, uimm5:$idx, ixlenimm:$sew),
[]>;

let HasVLOp = 1, BaseInstr = RI_VINSERT, HasVecPolicyOp = 1,
Constraints = "$rd = $rs1" in
def PseudoRI_VINSERT_ # mx :
Pseudo<(outs m.vrclass:$rd),
RISCVVPseudo<(outs m.vrclass:$rd),
(ins m.vrclass:$rs1, GPR:$rs2, uimm5:$idx, AVL:$vl,
ixlenimm:$sew, ixlenimm:$policy),
[]>,
RISCVVPseudo;
[]>;
}
}

Expand Down
30 changes: 12 additions & 18 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
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Original file line number Diff line number Diff line change
Expand Up @@ -243,10 +243,9 @@ let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvector",
}

class VPseudoVC_X<Operand OpClass, DAGOperand RS1Class> :
Pseudo<(outs),
RISCVVPseudo<(outs),
(ins OpClass:$op1, payload5:$rs2, payload5:$rd, RS1Class:$r1,
AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
Expand All @@ -255,10 +254,9 @@ class VPseudoVC_X<Operand OpClass, DAGOperand RS1Class> :
}

class VPseudoVC_XV<Operand OpClass, VReg RS2Class, DAGOperand RS1Class> :
Pseudo<(outs),
RISCVVPseudo<(outs),
(ins OpClass:$op1, payload5:$rd, RS2Class:$rs2, RS1Class:$r1,
AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
Expand All @@ -268,10 +266,9 @@ class VPseudoVC_XV<Operand OpClass, VReg RS2Class, DAGOperand RS1Class> :

class VPseudoVC_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
DAGOperand RS1Class> :
Pseudo<(outs),
RISCVVPseudo<(outs),
(ins OpClass:$op1, RDClass:$rd, RS2Class:$rs2, RS1Class:$r1,
AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
Expand All @@ -280,10 +277,9 @@ class VPseudoVC_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
}

class VPseudoVC_V_X<Operand OpClass, VReg RDClass, DAGOperand RS1Class> :
Pseudo<(outs RDClass:$rd),
RISCVVPseudo<(outs RDClass:$rd),
(ins OpClass:$op1, payload5:$rs2, RS1Class:$r1,
AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
Expand All @@ -293,10 +289,9 @@ class VPseudoVC_V_X<Operand OpClass, VReg RDClass, DAGOperand RS1Class> :

class VPseudoVC_V_XV<Operand OpClass, VReg RDClass, VReg RS2Class,
DAGOperand RS1Class> :
Pseudo<(outs RDClass:$rd),
RISCVVPseudo<(outs RDClass:$rd),
(ins OpClass:$op1, RS2Class:$rs2, RS1Class:$r1,
AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
Expand All @@ -306,10 +301,9 @@ class VPseudoVC_V_XV<Operand OpClass, VReg RDClass, VReg RS2Class,

class VPseudoVC_V_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
DAGOperand RS1Class> :
Pseudo<(outs RDClass:$rd),
RISCVVPseudo<(outs RDClass:$rd),
(ins OpClass:$op1, RDClass:$rs3, RS2Class:$rs2, RS1Class:$r1,
AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
AVL:$vl, sew:$sew), []> {
let mayLoad = 0;
let mayStore = 0;
let HasVLOp = 1;
Expand Down
10 changes: 4 additions & 6 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
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Original file line number Diff line number Diff line change
Expand Up @@ -230,9 +230,8 @@ class ZvkMxSet<string vd_lmul> {
}

class VPseudoBinaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass> :
Pseudo<(outs RetClass:$rd_wb),
(ins RetClass:$rd, OpClass:$rs2, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
RISCVVPseudo<(outs RetClass:$rd_wb),
(ins RetClass:$rd, OpClass:$rs2, AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
Expand All @@ -246,10 +245,9 @@ class VPseudoBinaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass> :
class VPseudoTernaryNoMask_Zvk<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class> :
Pseudo<(outs RetClass:$rd_wb),
RISCVVPseudo<(outs RetClass:$rd_wb),
(ins RetClass:$rd, Op1Class:$rs2, Op2Class:$rs1,
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
Expand Down
6 changes: 1 addition & 5 deletions llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,6 @@ namespace {
class RISCVVLOptimizer : public MachineFunctionPass {
const MachineRegisterInfo *MRI;
const MachineDominatorTree *MDT;
const TargetInstrInfo *TII;

public:
static char ID;
Expand Down Expand Up @@ -1292,8 +1291,7 @@ bool RISCVVLOptimizer::isCandidate(const MachineInstr &MI) const {
return false;
}

assert(!RISCVII::elementsDependOnVL(
TII->get(RISCV::getRVVMCOpcode(MI.getOpcode())).TSFlags) &&
assert(!RISCVII::elementsDependOnVL(MI.getDesc().TSFlags) &&
"Instruction shouldn't be supported if elements depend on VL");

assert(MI.getOperand(0).isReg() &&
Expand Down Expand Up @@ -1497,8 +1495,6 @@ bool RISCVVLOptimizer::runOnMachineFunction(MachineFunction &MF) {
if (!ST.hasVInstructions())
return false;

TII = ST.getInstrInfo();

// For each instruction that defines a vector, compute what VL its
// downstream users demand.
for (MachineBasicBlock *MBB : post_order(&MF)) {
Expand Down
15 changes: 7 additions & 8 deletions llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
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Expand Up @@ -91,8 +91,7 @@ bool RISCVVectorPeephole::hasSameEEW(const MachineInstr &User,
User.getOperand(RISCVII::getSEWOpNum(User.getDesc())).getImm();
unsigned SrcLog2SEW =
Src.getOperand(RISCVII::getSEWOpNum(Src.getDesc())).getImm();
unsigned SrcLog2EEW = RISCV::getDestLog2EEW(
TII->get(RISCV::getRVVMCOpcode(Src.getOpcode())), SrcLog2SEW);
unsigned SrcLog2EEW = RISCV::getDestLog2EEW(Src.getDesc(), SrcLog2SEW);
return SrcLog2EEW == UserLog2SEW;
}

Expand Down Expand Up @@ -170,8 +169,8 @@ bool RISCVVectorPeephole::tryToReduceVL(MachineInstr &MI) const {
if (!hasSameEEW(MI, *Src))
continue;

bool ElementsDependOnVL = RISCVII::elementsDependOnVL(
TII->get(RISCV::getRVVMCOpcode(Src->getOpcode())).TSFlags);
bool ElementsDependOnVL =
RISCVII::elementsDependOnVL(Src->getDesc().TSFlags);
if (ElementsDependOnVL || Src->mayRaiseFPException())
continue;

Expand Down Expand Up @@ -760,11 +759,11 @@ bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const {
else
return false;

unsigned RVVTSFlags =
TII->get(RISCV::getRVVMCOpcode(True.getOpcode())).TSFlags;
if (RISCVII::elementsDependOnVL(RVVTSFlags) && !TrueVL.isIdenticalTo(MinVL))
if (RISCVII::elementsDependOnVL(True.getDesc().TSFlags) &&
!TrueVL.isIdenticalTo(MinVL))
return false;
if (RISCVII::elementsDependOnMask(RVVTSFlags) && !isAllOnesMask(Mask))
if (RISCVII::elementsDependOnMask(True.getDesc().TSFlags) &&
!isAllOnesMask(Mask))
return false;

// Use a tumu policy, relaxing it to tail agnostic provided that the passthru
Expand Down
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