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Merged
merged 1 commit into from
Jul 22, 2025
Merged

Revert "[AMDGPU] Recognise bitmask operations as srcmods" #150000

merged 1 commit into from
Jul 22, 2025
+282 −1,232

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chrisjbris
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Reverts #149110 due to various buildbot failures.

@chrisjbris chrisjbris self-assigned this Jul 22, 2025
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llvmbot commented Jul 22, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: Chris Jackson (chrisjbris)

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Reverts llvm/llvm-project#149110 due to various buildbot failures.

Patch is 85.75 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/150000.diff

5 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp (-32)
  • (modified) llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll (+26-15)
  • (removed) llvm/test/CodeGen/AMDGPU/integer-select-src-modifiers.ll (-1011)
  • (modified) llvm/test/CodeGen/AMDGPU/saddsat.ll (+31-21)
  • (modified) llvm/test/CodeGen/AMDGPU/ssubsat.ll (+225-153)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index fe0e7eb279486..00c7f0eb6e9f1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -3059,38 +3059,6 @@ bool AMDGPUDAGToDAGISel::SelectVOP3ModsImpl(SDValue In, SDValue &Src,
     Src = Src.getOperand(0);
   }
 
-  // Convert various sign-bit masks to src mods. Currently disabled for 16-bit
-  // types as the codegen replaces the operand without adding a srcmod.
-  // This is intentionally finding the cases where we are performing float neg
-  // and abs on int types, the goal is not to obtain two's complement neg or
-  // abs.
-  // TODO: Add 16-bit support.
-  unsigned Opc = Src->getOpcode();
-  EVT VT = Src.getValueType();
-  if ((Opc != ISD::AND && Opc != ISD::OR && Opc != ISD::XOR) ||
-      (VT != MVT::i32 && VT != MVT::v2i32 && VT != MVT::i64))
-    return true;
-
-  ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Src->getOperand(1));
-  if (!CRHS)
-    return true;
-
-  // Recognise (xor a, 0x80000000) as NEG SrcMod.
-  // Recognise (and a, 0x7fffffff) as ABS SrcMod.
-  // Recognise (or a, 0x80000000) as NEG+ABS SrcModifiers.
-  if (Opc == ISD::XOR && CRHS->getAPIntValue().isSignMask()) {
-    Mods |= SISrcMods::NEG;
-    Src = Src.getOperand(0);
-  } else if (Opc == ISD::AND && AllowAbs &&
-             CRHS->getAPIntValue().isMaxSignedValue()) {
-    Mods |= SISrcMods::ABS;
-    Src = Src.getOperand(0);
-  } else if (Opc == ISD::OR && AllowAbs && CRHS->getAPIntValue().isSignMask()) {
-    Mods |= SISrcMods::ABS;
-    Mods |= SISrcMods::NEG;
-    Src = Src.getOperand(0);
-  }
-
   return true;
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
index 5674ae328406d..1b092b283290a 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
@@ -349,24 +349,29 @@ define i32 @select_fneg_xor_select_i32(i1 %cond0, i1 %cond1, i32 %arg0, i32 %arg
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
-; GCN-NEXT:    v_and_b32_e32 v1, 1, v1
+; GCN-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
-; GCN-NEXT:    v_cndmask_b32_e64 v0, -v2, v3, vcc
+; GCN-NEXT:    v_and_b32_e32 v1, 1, v1
+; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc
+; GCN-NEXT:    v_xor_b32_e32 v2, 0x80000000, v0
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, -v0, vcc
+; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: select_fneg_xor_select_i32:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
 ; GFX11-NEXT:    v_and_b32_e32 v1, 1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
 ; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, -v2, v3, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc_lo
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
 ; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, v0, -v0, vcc_lo
+; GFX11-NEXT:    v_xor_b32_e32 v2, 0x80000000, v0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %fneg0 = xor i32 %arg0, -2147483648
   %select0 = select i1 %cond0, i32 %arg1, i32 %fneg0
@@ -545,25 +550,31 @@ define i64 @select_fneg_xor_select_i64(i1 %cond0, i1 %cond1, i64 %arg0, i64 %arg
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
-; GCN-NEXT:    v_and_b32_e32 v1, 1, v1
+; GCN-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; GCN-NEXT:    v_and_b32_e32 v1, 1, v1
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc
-; GCN-NEXT:    v_cndmask_b32_e64 v2, -v3, v5, vcc
+; GCN-NEXT:    v_cndmask_b32_e32 v2, v3, v5, vcc
+; GCN-NEXT:    v_xor_b32_e32 v3, 0x80000000, v2
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, -v2, vcc
+; GCN-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: select_fneg_xor_select_i64:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX11-NEXT:    v_and_b32_e32 v1, 1, v1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
 ; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT:    v_dual_cndmask_b32 v0, v2, v4 :: v_dual_and_b32 v1, 1, v1
-; GFX11-NEXT:    v_cndmask_b32_e64 v2, -v3, v5, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e32 v2, v3, v5, vcc_lo
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
 ; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e64 v1, v2, -v2, vcc_lo
+; GFX11-NEXT:    v_xor_b32_e32 v3, 0x80000000, v2
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %fneg0 = xor i64 %arg0, 9223372036854775808
   %select0 = select i1 %cond0, i64 %arg1, i64 %fneg0
diff --git a/llvm/test/CodeGen/AMDGPU/integer-select-src-modifiers.ll b/llvm/test/CodeGen/AMDGPU/integer-select-src-modifiers.ll
deleted file mode 100644
index b3c7ac80dd014..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/integer-select-src-modifiers.ll
+++ /dev/null
@@ -1,1011 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GFX7 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
-
-define i32 @fneg_select_i32_1(i32 %cond, i32 %a, i32 %b) {
-; GCN-LABEL: fneg_select_i32_1:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, -v1, vcc
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: fneg_select_i32_1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, v2, -v1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %neg.a = xor i32 %a, u0x80000000
-  %cmp = icmp eq i32 %cond, zeroinitializer
-  %select = select i1 %cmp, i32 %neg.a, i32 %b
-  ret i32 %select
-}
-
-define i32 @fneg_select_i32_2(i32 %cond, i32 %a, i32 %b) {
-; GCN-LABEL: fneg_select_i32_2:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GCN-NEXT:    v_cndmask_b32_e64 v0, -v1, v2, vcc
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: fneg_select_i32_2:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, -v1, v2, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %neg.a = xor i32 %a, u0x80000000
-  %cmp = icmp eq i32 %cond, zeroinitializer
-  %select = select i1 %cmp, i32 %b, i32 %neg.a
-  ret i32 %select
-}
-
-define i32 @fneg_select_i32_both(i32 %cond, i32 %a, i32 %b) {
-; GCN-LABEL: fneg_select_i32_both:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GCN-NEXT:    v_cndmask_b32_e64 v0, -v2, -v1, vcc
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: fneg_select_i32_both:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, -v2, -v1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %neg.a = xor i32 %a, u0x80000000
-  %neg.b = xor i32 %b, u0x80000000
-  %cmp = icmp eq i32 %cond, zeroinitializer
-  %select = select i1 %cmp, i32 %neg.a, i32 %neg.b
-  ret i32 %select
-}
-
-define i32 @fneg_1_fabs_2_select_i32(i32 %cond, i32 %a, i32 %b) {
-; GCN-LABEL: fneg_1_fabs_2_select_i32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GCN-NEXT:    v_cndmask_b32_e64 v0, |v1|, -v1, vcc
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: fneg_1_fabs_2_select_i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, |v1|, -v1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %neg.a = xor i32 %a, u0x80000000
-  %abs.b = and i32 %a, u0x7fffffff
-  %cmp = icmp eq i32 %cond, zeroinitializer
-  %select = select i1 %cmp, i32 %neg.a, i32 %abs.b
-  ret i32 %select
-}
-
-define i32 @s_fneg_select_i32_1(i32 inreg %cond, i32 inreg %a, i32 inreg %b) {
-; GCN-LABEL: s_fneg_select_i32_1:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    s_xor_b32 s4, s17, 0x80000000
-; GCN-NEXT:    s_cmp_eq_u32 s16, 0
-; GCN-NEXT:    s_cselect_b32 s4, s4, s18
-; GCN-NEXT:    v_mov_b32_e32 v0, s4
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: s_fneg_select_i32_1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_xor_b32 s1, s1, 0x80000000
-; GFX11-NEXT:    s_cmp_eq_u32 s0, 0
-; GFX11-NEXT:    s_cselect_b32 s0, s1, s2
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    v_mov_b32_e32 v0, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %neg.a = xor i32 %a, u0x80000000
-  %cmp = icmp eq i32 %cond, zeroinitializer
-  %select = select i1 %cmp, i32 %neg.a, i32 %b
-  ret i32 %select
-}
-
-define i32 @s_fneg_1_fabs_2_select_i32(i32 inreg %cond, i32 %a, i32 %b) {
-; GCN-LABEL: s_fneg_1_fabs_2_select_i32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    s_cmp_eq_u32 s16, 0
-; GCN-NEXT:    s_cselect_b64 s[4:5], -1, 0
-; GCN-NEXT:    v_cndmask_b32_e64 v0, |v0|, -v0, s[4:5]
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: s_fneg_1_fabs_2_select_i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_cmp_eq_u32 s0, 0
-; GFX11-NEXT:    s_cselect_b32 s0, -1, 0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, |v0|, -v0, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %neg.a = xor i32 %a, u0x80000000
-  %abs.b = and i32 %a, u0x7fffffff
-  %cmp = icmp eq i32 %cond, zeroinitializer
-  %select = select i1 %cmp, i32 %neg.a, i32 %abs.b
-  ret i32 %select
-}
-
-define <2 x i32> @fneg_select_v2i32_1(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {
-; GCN-LABEL: fneg_select_v2i32_1:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GCN-NEXT:    v_cndmask_b32_e64 v0, v4, -v2, vcc
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v1, v5, -v3, vcc
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: fneg_select_v2i32_1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, v4, -v2, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-NEXT:    v_cndmask_b32_e64 v1, v5, -v3, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %neg.a = xor <2 x i32> %a, splat (i32 u0x80000000)
-  %cmp = icmp eq <2 x i32> %cond, zeroinitializer
-  %select = select <2 x i1> %cmp, <2 x i32> %neg.a, <2 x i32> %b
-  ret <2 x i32> %select
-}
-
-define <2 x i32> @fneg_select_v2i32_2(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {
-; GCN-LABEL: fneg_select_v2i32_2:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GCN-NEXT:    v_cndmask_b32_e64 v0, -v2, v4, vcc
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v1, -v3, v5, vcc
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: fneg_select_v2i32_2:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, -v2, v4, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-NEXT:    v_cndmask_b32_e64 v1, -v3, v5, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %neg.a = xor <2 x i32> %a, splat (i32 u0x80000000)
-  %cmp = icmp eq <2 x i32> %cond, zeroinitializer
-  %select = select <2 x i1> %cmp, <2 x i32> %b, <2 x i32> %neg.a
-  ret <2 x i32> %select
-}
-
-define i32 @fabs_select_i32_1(i32 %cond, i32 %a, i32 %b) {
-; GCN-LABEL: fabs_select_i32_1:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, |v1|, vcc
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: fabs_select_i32_1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, v2, |v1|, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %neg.a = and i32 %a, u0x7fffffff
-  %cmp = icmp eq i32 %cond, zeroinitializer
-  %select = select i1 %cmp, i32 %neg.a, i32 %b
-  ret i32 %select
-}
-
-define i32 @fabs_select_i32_2(i32 %cond, i32 %a, i32 %b) {
-; GCN-LABEL: fabs_select_i32_2:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GCN-NEXT:    v_cndmask_b32_e64 v0, |v1|, v2, vcc
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: fabs_select_i32_2:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, |v1|, v2, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %neg.a = and i32 %a, u0x7fffffff
-  %cmp = icmp eq i32 %cond, zeroinitializer
-  %select = select i1 %cmp, i32 %b, i32 %neg.a
-  ret i32 %select
-}
-
-define <2 x i32> @fneg_1_fabs_2_select_v2i32(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {
-; GCN-LABEL: fneg_1_fabs_2_select_v2i32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GCN-NEXT:    v_cndmask_b32_e64 v0, -v2, |v2|, vcc
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v1, -v3, |v3|, vcc
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: fneg_1_fabs_2_select_v2i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, -v2, |v2|, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-NEXT:    v_cndmask_b32_e64 v1, -v3, |v3|, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %neg.a = xor <2 x i32> %a, splat (i32 u0x80000000)
-  %abs.b = and <2 x i32> %a, splat (i32 u0x7fffffff)
-  %cmp = icmp eq <2 x i32> %cond, zeroinitializer
-  %select = select <2 x i1> %cmp, <2 x i32> %abs.b, <2 x i32> %neg.a
-  ret <2 x i32> %select
-}
-
-define i32 @fneg_fabs_select_i32_1(i32 %cond, i32 %a, i32 %b) {
-; GCN-LABEL: fneg_fabs_select_i32_1:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, -|v1|, vcc
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: fneg_fabs_select_i32_1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, v2, -|v1|, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %neg.a = or i32 %a, u0x80000000
-  %cmp = icmp eq i32 %cond, zeroinitializer
-  %select = select i1 %cmp, i32 %neg.a, i32 %b
-  ret i32 %select
-}
-
-define i32 @fneg_fabs_select_i32_2(i32 %cond, i32 %a, i32 %b) {
-; GCN-LABEL: fneg_fabs_select_i32_2:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GCN-NEXT:    v_cndmask_b32_e64 v0, -|v1|, v2, vcc
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: fneg_fabs_select_i32_2:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, -|v1|, v2, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %neg.a = or i32 %a, u0x80000000
-  %cmp = icmp eq i32 %cond, zeroinitializer
-  %select = select i1 %cmp, i32 %b, i32 %neg.a
-  ret i32 %select
-}
-
-define <2 x i32> @fneg_fabs_select_v2i32_1(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {
-; GCN-LABEL: fneg_fabs_select_v2i32_1:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GCN-NEXT:    v_cndmask_b32_e64 v0, v4, -|v2|, vcc
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v1, v5, -|v3|, vcc
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: fneg_fabs_select_v2i32_1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, v4, -|v2|, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-NEXT:    v_cndmask_b32_e64 v1, v5, -|v3|, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %neg.a = or <2 x i32> %a, splat (i32 u0x80000000)
-  %cmp = icmp eq <2 x i32> %cond, zeroinitializer
-  %select = select <2 x i1> %cmp, <2 x i32> %neg.a, <2 x i32> %b
-  ret <2 x i32> %select
-}
-
-define <2 x i32> @fneg_fabs_select_v2i32_2(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {
-; GCN-LABEL: fneg_fabs_select_v2i32_2:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GCN-NEXT:    v_cndmask_b32_e64 v0, -|v2|, v4, vcc
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v1, -|v3|, v5, vcc
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: fneg_fabs_select_v2i32_2:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, -|v2|, v4, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-NEXT:    v_cndmask_b32_e64 v1, -|v3|, v5, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %neg.a = or <2 x i32> %a, splat (i32 u0x80000000)
-  %cmp = icmp eq <2 x i32> %cond, zeroinitializer
-  %select = select <2 x i1> %cmp, <2 x i32> %b, <2 x i32> %neg.a
-  ret <2 x i32> %select
-}
-
-
-define <2 x i32> @s_fneg_select_v2i32_1(<2 x i32> inreg %cond, <2 x i32> inreg %a, <2 x i32> inreg %b) {
-; GCN-LABEL: s_fneg_select_v2i32_1:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    s_xor_b32 s4, s19, 0x80000000
-; GCN-NEXT:    s_xor_b32 s5, s18, 0x80000000
-; GCN-NEXT:    s_cmp_eq_u32 s16, 0
-; GCN-NEXT:    s_cselect_b32 s5, s5, s20
-; GCN-NEXT:    s_cmp_eq_u32 s17, 0
-; GCN-NEXT:    s_cselect_b32 s4, s4, s21
-; GCN-NEXT:    v_mov_b32_e32 v0, s5
-; GCN-NEXT:    v_mov_b32_e32 v1, s4
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: s_fneg_select_v2i32_1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_xor_b32 s3, s3, 0x80000000
-; GFX11-NEXT:    s_xor_b32 s2, s2, 0x80000000
-; GFX11-NEXT:    s_cmp_eq_u32 s0, 0
-; GFX1...
[truncated]

@chrisjbris chrisjbris merged commit b3e016e into main Jul 22, 2025
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@chrisjbris chrisjbris deleted the revert-149110-chrisjbris/integer_select_source_modifiers_VOP branch July 22, 2025 11:16
@chrisjbris chrisjbris added the skip-precommit-approval PR for CI feedback, not intended for review label Jul 22, 2025
mahesh-attarde pushed a commit to mahesh-attarde/llvm-project that referenced this pull request Jul 28, 2025
@chrisjbris @mahesh-attarde
Revert "[AMDGPU] Recognise bitmask operations as srcmods" (llvm#150000)
d3d09a7 
Reverts llvm#149110 due to various buildbot failures.
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