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[DAG] visitFREEZE - replace multiple frozen/unfrozen uses of an SDValue with just the frozen node #150017

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Merged
RKSimon merged 7 commits into from
Aug 5, 2025
Merged

[DAG] visitFREEZE - replace multiple frozen/unfrozen uses of an SDValue with just the frozen node #150017

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f9eadbc
[DAG] visitFREEZE - replace multiple frozen/unfrozen uses of an SDVal…
RKSimon Jul 22, 2025
7aab203
Merge branch 'upstream' into dag-freeze-extrause
RKSimon Jul 31, 2025
42dd989
Merge branch 'main' into dag-freeze-extrause
RKSimon Aug 1, 2025
82d510d
Tidyup SDValue initialization
RKSimon Aug 1, 2025
195b164
Merge branch 'main' into dag-freeze-extrause
RKSimon Aug 4, 2025
3727f02
Merge branch 'main' into dag-freeze-extrause
RKSimon Aug 5, 2025
833f797
Test regeneration
RKSimon Aug 5, 2025
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20 changes: 12 additions & 8 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4075,18 +4075,11 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
unsigned BitWidth = VT.getScalarSizeInBits();
SDLoc DL(N);

auto PeekThroughFreeze = [](SDValue N) {
if (N->getOpcode() == ISD::FREEZE && N.hasOneUse())
return N->getOperand(0);
return N;
};

if (SDValue V = foldSubCtlzNot<EmptyMatchContext>(N, DAG))
return V;

// fold (sub x, x) -> 0
// FIXME: Refactor this and xor and other similar operations together.
if (PeekThroughFreeze(N0) == PeekThroughFreeze(N1))
if (N0 == N1)
return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);

// fold (sub c1, c2) -> c3
Expand Down Expand Up @@ -16756,6 +16749,17 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
if (DAG.isGuaranteedNotToBeUndefOrPoison(N0, /*PoisonOnly*/ false))
return N0;

// If we have frozen and unfrozen users of N0, update so everything uses N.
if (!N0.isUndef() && !N0.hasOneUse()) {
SDValue FrozenN0(N, 0);
DAG.ReplaceAllUsesOfValueWith(N0, FrozenN0);
// ReplaceAllUsesOfValueWith will have also updated the use in N, thus
// creating a cycle in a DAG. Let's undo that by mutating the freeze.
assert(N->getOperand(0) == FrozenN0 && "Expected cycle in DAG");
DAG.UpdateNodeOperands(N, N0);
return FrozenN0;
}

// We currently avoid folding freeze over SRA/SRL, due to the problems seen
// with (freeze (assert ext)) blocking simplifications of SRA/SRL. See for
// example https://reviews.llvm.org/D136529#4120959.
Expand Down
7 changes: 0 additions & 7 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Expand Up @@ -775,13 +775,6 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(

break;
}
case ISD::FREEZE: {
SDValue N0 = Op.getOperand(0);
if (DAG.isGuaranteedNotToBeUndefOrPoison(N0, DemandedElts,
/*PoisonOnly=*/false, Depth + 1))
return N0;
break;
}
case ISD::AND: {
LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/AArch64/vselect-ext.ll
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Expand Up @@ -175,12 +175,12 @@ define <8 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v8i32_from_v8i1
; CHECK: ; %bb.0:
; CHECK-NEXT: bic.8h v0, #128, lsl #8
; CHECK-NEXT: movi.4s v1, #10
; CHECK-NEXT: ushll.4s v2, v0, #0
; CHECK-NEXT: ushll2.4s v0, v0, #0
; CHECK-NEXT: cmhi.4s v3, v2, v1
; CHECK-NEXT: cmhi.4s v1, v0, v1
; CHECK-NEXT: and.16b v1, v1, v0
; CHECK-NEXT: and.16b v0, v3, v2
; CHECK-NEXT: ushll2.4s v2, v0, #0
; CHECK-NEXT: ushll.4s v0, v0, #0
; CHECK-NEXT: cmhi.4s v3, v0, v1
; CHECK-NEXT: cmhi.4s v1, v2, v1
; CHECK-NEXT: and.16b v1, v1, v2
; CHECK-NEXT: and.16b v0, v3, v0
; CHECK-NEXT: ret
%ext = zext <8 x i15> %a to <8 x i32>
%cmp = icmp ugt <8 x i15> %a, <i15 10, i15 10, i15 10, i15 10, i15 10, i15 10, i15 10, i15 10>
Expand Down Expand Up @@ -289,12 +289,12 @@ define <8 x i32> @same_zext_used_in_cmp_eq_and_select_v8i32_from_v8i13(<8 x i13>
; CHECK: ; %bb.0:
; CHECK-NEXT: bic.8h v0, #224, lsl #8
; CHECK-NEXT: movi.4s v1, #10
; CHECK-NEXT: ushll.4s v2, v0, #0
; CHECK-NEXT: ushll2.4s v0, v0, #0
; CHECK-NEXT: cmeq.4s v3, v2, v1
; CHECK-NEXT: cmeq.4s v1, v0, v1
; CHECK-NEXT: and.16b v1, v1, v0
; CHECK-NEXT: and.16b v0, v3, v2
; CHECK-NEXT: ushll2.4s v2, v0, #0
; CHECK-NEXT: ushll.4s v0, v0, #0
; CHECK-NEXT: cmeq.4s v3, v0, v1
; CHECK-NEXT: cmeq.4s v1, v2, v1
; CHECK-NEXT: and.16b v1, v1, v2
; CHECK-NEXT: and.16b v0, v3, v0
; CHECK-NEXT: ret
%ext = zext <8 x i13> %a to <8 x i32>
%cmp = icmp eq <8 x i13> %a, <i13 10, i13 10, i13 10, i13 10, i13 10, i13 10, i13 10, i13 10>
Expand Down Expand Up @@ -429,17 +429,17 @@ define <8 x i32> @same_sext_used_in_cmp_eq_and_select_v8i32(<8 x i16> %a) {
define <8 x i32> @same_sext_used_in_cmp_eq_and_select_v8i32_from_v8i13(<8 x i13> %a) {
; CHECK-LABEL: same_sext_used_in_cmp_eq_and_select_v8i32_from_v8i13:
; CHECK: ; %bb.0:
; CHECK-NEXT: ushll2.4s v2, v0, #0
; CHECK-NEXT: ushll.4s v0, v0, #0
; CHECK-NEXT: ushll.4s v2, v0, #0
; CHECK-NEXT: ushll2.4s v0, v0, #0
; CHECK-NEXT: movi.4s v1, #10
; CHECK-NEXT: shl.4s v0, v0, #19
; CHECK-NEXT: shl.4s v2, v2, #19
; CHECK-NEXT: sshr.4s v0, v0, #19
; CHECK-NEXT: sshr.4s v2, v2, #19
; CHECK-NEXT: cmeq.4s v3, v0, v1
; CHECK-NEXT: cmeq.4s v1, v2, v1
; CHECK-NEXT: and.16b v1, v1, v2
; CHECK-NEXT: and.16b v0, v3, v0
; CHECK-NEXT: cmeq.4s v3, v2, v1
; CHECK-NEXT: cmeq.4s v1, v0, v1
; CHECK-NEXT: and.16b v1, v1, v0
; CHECK-NEXT: and.16b v0, v3, v2
; CHECK-NEXT: ret
%ext = sext <8 x i13> %a to <8 x i32>
%cmp = icmp eq <8 x i13> %a, <i13 10, i13 10, i13 10, i13 10, i13 10, i13 10, i13 10, i13 10>
Expand Down Expand Up @@ -493,17 +493,17 @@ entry:
define <8 x i32> @same_sext_used_in_cmp_unsigned_pred_and_select_v8i32_from_v8i15(<8 x i15> %a) {
; CHECK-LABEL: same_sext_used_in_cmp_unsigned_pred_and_select_v8i32_from_v8i15:
; CHECK: ; %bb.0:
; CHECK-NEXT: ushll2.4s v2, v0, #0
; CHECK-NEXT: ushll.4s v0, v0, #0
; CHECK-NEXT: ushll.4s v2, v0, #0
; CHECK-NEXT: ushll2.4s v0, v0, #0
; CHECK-NEXT: movi.4s v1, #10
; CHECK-NEXT: shl.4s v0, v0, #17
; CHECK-NEXT: shl.4s v2, v2, #17
; CHECK-NEXT: sshr.4s v0, v0, #17
; CHECK-NEXT: sshr.4s v2, v2, #17
; CHECK-NEXT: cmge.4s v3, v0, v1
; CHECK-NEXT: cmge.4s v1, v2, v1
; CHECK-NEXT: and.16b v1, v1, v2
; CHECK-NEXT: and.16b v0, v3, v0
; CHECK-NEXT: cmge.4s v3, v2, v1
; CHECK-NEXT: cmge.4s v1, v0, v1
; CHECK-NEXT: and.16b v1, v1, v0
; CHECK-NEXT: and.16b v0, v3, v2
; CHECK-NEXT: ret
%ext = sext <8 x i15> %a to <8 x i32>
%cmp = icmp sge <8 x i15> %a, <i15 10, i15 10, i15 10, i15 10, i15 10, i15 10, i15 10, i15 10>
Expand Down
10 changes: 6 additions & 4 deletions llvm/test/CodeGen/AMDGPU/div_i128.ll
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Expand Up @@ -495,8 +495,9 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-O0-NEXT: v_and_b32_e64 v6, 1, v6
; GFX9-O0-NEXT: v_cmp_eq_u32_e64 s[8:9], v6, 1
; GFX9-O0-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9]
; GFX9-O0-NEXT: s_mov_b64 s[4:5], -1
; GFX9-O0-NEXT: s_xor_b64 s[4:5], s[8:9], s[4:5]
; GFX9-O0-NEXT: s_mov_b64 s[14:15], -1
; GFX9-O0-NEXT: s_mov_b64 s[4:5], s[8:9]
; GFX9-O0-NEXT: s_xor_b64 s[4:5], s[4:5], s[14:15]
Comment on lines +498 to +500
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@arsenm arsenm Jul 31, 2025

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This is worse in a weird way, but I suppose it is -O0

; GFX9-O0-NEXT: v_mov_b32_e32 v6, v5
; GFX9-O0-NEXT: s_mov_b32 s14, s13
; GFX9-O0-NEXT: v_xor_b32_e64 v6, v6, s14
Expand Down Expand Up @@ -2679,8 +2680,9 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-O0-NEXT: v_and_b32_e64 v6, 1, v6
; GFX9-O0-NEXT: v_cmp_eq_u32_e64 s[8:9], v6, 1
; GFX9-O0-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9]
; GFX9-O0-NEXT: s_mov_b64 s[4:5], -1
; GFX9-O0-NEXT: s_xor_b64 s[4:5], s[8:9], s[4:5]
; GFX9-O0-NEXT: s_mov_b64 s[14:15], -1
; GFX9-O0-NEXT: s_mov_b64 s[4:5], s[8:9]
; GFX9-O0-NEXT: s_xor_b64 s[4:5], s[4:5], s[14:15]
; GFX9-O0-NEXT: v_mov_b32_e32 v6, v5
; GFX9-O0-NEXT: s_mov_b32 s14, s13
; GFX9-O0-NEXT: v_xor_b32_e64 v6, v6, s14
Expand Down
75 changes: 12 additions & 63 deletions llvm/test/CodeGen/AMDGPU/freeze.ll
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Expand Up @@ -5692,10 +5692,6 @@ define void @freeze_v3i16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX6-SDAG-NEXT: s_mov_b32 s5, s6
; GFX6-SDAG-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX6-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX6-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-SDAG-NEXT: v_or_b32_e32 v0, v0, v4
; GFX6-SDAG-NEXT: buffer_store_short v1, v[2:3], s[4:7], 0 addr64 offset:4
; GFX6-SDAG-NEXT: buffer_store_dword v0, v[2:3], s[4:7], 0 addr64
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0)
Expand Down Expand Up @@ -5725,10 +5721,6 @@ define void @freeze_v3i16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX7-SDAG-NEXT: s_mov_b32 s5, s6
; GFX7-SDAG-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v0, v4
; GFX7-SDAG-NEXT: buffer_store_short v1, v[2:3], s[4:7], 0 addr64 offset:4
; GFX7-SDAG-NEXT: buffer_store_dword v0, v[2:3], s[4:7], 0 addr64
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -6351,10 +6343,6 @@ define void @freeze_v3f16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX6-SDAG-NEXT: s_mov_b32 s5, s6
; GFX6-SDAG-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX6-SDAG-NEXT: v_and_b32_e32 v4, 0xffff, v0
; GFX6-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX6-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-SDAG-NEXT: v_or_b32_e32 v0, v4, v0
; GFX6-SDAG-NEXT: buffer_store_short v1, v[2:3], s[4:7], 0 addr64 offset:4
; GFX6-SDAG-NEXT: buffer_store_dword v0, v[2:3], s[4:7], 0 addr64
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0)
Expand Down Expand Up @@ -6384,10 +6372,6 @@ define void @freeze_v3f16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX7-SDAG-NEXT: s_mov_b32 s5, s6
; GFX7-SDAG-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: v_and_b32_e32 v4, 0xffff, v0
; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX7-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v4, v0
; GFX7-SDAG-NEXT: buffer_store_short v1, v[2:3], s[4:7], 0 addr64 offset:4
; GFX7-SDAG-NEXT: buffer_store_dword v0, v[2:3], s[4:7], 0 addr64
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -12347,14 +12331,9 @@ define void @freeze_v3i8(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX6-SDAG-NEXT: s_mov_b32 s5, s6
; GFX6-SDAG-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX6-SDAG-NEXT: v_lshrrev_b32_e32 v4, 8, v0
; GFX6-SDAG-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX6-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX6-SDAG-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX6-SDAG-NEXT: v_or_b32_e32 v0, v0, v4
; GFX6-SDAG-NEXT: buffer_store_byte v1, v[2:3], s[4:7], 0 addr64 offset:2
; GFX6-SDAG-NEXT: buffer_store_short v0, v[2:3], s[4:7], 0 addr64
; GFX6-SDAG-NEXT: buffer_store_byte v1, v[2:3], s[4:7], 0 addr64 offset:2
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
;
Expand Down Expand Up @@ -12392,14 +12371,9 @@ define void @freeze_v3i8(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX7-SDAG-NEXT: s_mov_b32 s5, s6
; GFX7-SDAG-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v4, 8, v0
; GFX7-SDAG-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-SDAG-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v0, v4
; GFX7-SDAG-NEXT: buffer_store_byte v1, v[2:3], s[4:7], 0 addr64 offset:2
; GFX7-SDAG-NEXT: buffer_store_short v0, v[2:3], s[4:7], 0 addr64
; GFX7-SDAG-NEXT: buffer_store_byte v1, v[2:3], s[4:7], 0 addr64 offset:2
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
Expand Down Expand Up @@ -12474,11 +12448,7 @@ define void @freeze_v3i8(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: global_load_dword v0, v[0:1], off
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX10-SDAG-NEXT: v_lshrrev_b16 v1, 8, v0
; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX10-SDAG-NEXT: v_lshlrev_b16 v1, 8, v1
; GFX10-SDAG-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-SDAG-NEXT: global_store_byte v[2:3], v4, off offset:2
; GFX10-SDAG-NEXT: global_store_byte_d16_hi v[2:3], v0, off offset:2
; GFX10-SDAG-NEXT: global_store_short v[2:3], v0, off
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
Expand All @@ -12499,36 +12469,15 @@ define void @freeze_v3i8(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
; GFX10-GISEL-NEXT: global_store_byte_d16_hi v[2:3], v0, off offset:2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: freeze_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: global_load_b32 v1, v[0:1], off
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.h, 0
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b16 v0.l, 8, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.h
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_clause 0x1
; GFX11-SDAG-TRUE16-NEXT: global_store_b8 v[2:3], v4, off offset:2
; GFX11-SDAG-TRUE16-NEXT: global_store_b16 v[2:3], v0, off
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: freeze_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0:
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b16 v1, 8, v0
; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v0
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1
; GFX11-SDAG-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
; GFX11-SDAG-FAKE16-NEXT: s_clause 0x1
; GFX11-SDAG-FAKE16-NEXT: global_store_b8 v[2:3], v0, off offset:2
; GFX11-SDAG-FAKE16-NEXT: global_store_b16 v[2:3], v1, off
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-SDAG-LABEL: freeze_v3i8:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX11-SDAG-NEXT: s_clause 0x1
; GFX11-SDAG-NEXT: global_store_d16_hi_b8 v[2:3], v0, off offset:2
; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: freeze_v3i8:
; GFX11-GISEL: ; %bb.0:
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