[RISCV] Fix alignment when mixing rvc/norvc relax/norelax code

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -3177,6 +3177,17 @@ bool RISCVAsmParser::parseDirectiveOption() {
     if (Parser.parseEOL())
       return true;
 
+    auto &Streamer = getTargetStreamer().getStreamer();
+    auto *Assembler = Streamer.getAssemblerPtr();
+    auto *Section = Streamer.getCurrentSectionOnly();
+    // Update RVCEver status only if any instruction emitted.
+    if (Section->hasInstructions() && Assembler != nullptr &&
+        getSTI().hasFeature(RISCV::FeatureStdExtZca)) {
+      RISCVAsmBackend &MAB =
+          static_cast<RISCVAsmBackend &>(Assembler->getBackend());
+      MAB.setRVCEver(Section);
+    }
+
     getTargetStreamer().emitDirectiveOptionNoRVC();
     clearFeatureBits(RISCV::FeatureStdExtC, "c");
     clearFeatureBits(RISCV::FeatureStdExtZca, "zca");
@@ -3214,6 +3225,17 @@ bool RISCVAsmParser::parseDirectiveOption() {
     if (Parser.parseEOL())
       return true;
 
+    auto &Streamer = getTargetStreamer().getStreamer();
+    auto *Assembler = Streamer.getAssemblerPtr();
+    auto *Section = Streamer.getCurrentSectionOnly();
+    // Update RelaxEver status only if any instruction emitted.
+    if (Assembler != nullptr && Section->hasInstructions() &&
+        getSTI().hasFeature(RISCV::FeatureRelax)) {
+      RISCVAsmBackend &MAB =
+          static_cast<RISCVAsmBackend &>(Assembler->getBackend());
+      MAB.setRelaxEver(Section);
+    }
+
     getTargetStreamer().emitDirectiveOptionNoRelax();
     clearFeatureBits(RISCV::FeatureRelax, "relax");
     return false;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

@@ -309,9 +309,12 @@ bool RISCVAsmBackend::relaxAlign(MCFragment &F, unsigned &Size) {
   // Use default handling unless linker relaxation is enabled and the alignment
   // is larger than the nop size.
   const MCSubtargetInfo *STI = F.getSubtargetInfo();
-  if (!STI->hasFeature(RISCV::FeatureRelax))
+  if (!STI->hasFeature(RISCV::FeatureRelax) && !hasRelaxEver(F.getParent()))
     return false;
-  unsigned MinNopLen = STI->hasFeature(RISCV::FeatureStdExtZca) ? 2 : 4;
+  unsigned MinNopLen =
+      hasRVCEver(F.getParent()) || STI->hasFeature(RISCV::FeatureStdExtZca)
+          ? 2
+          : 4;
   if (F.getAlignment() <= MinNopLen)
     return false;
 

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h

@@ -12,8 +12,10 @@
 #include "MCTargetDesc/RISCVBaseInfo.h"
 #include "MCTargetDesc/RISCVFixupKinds.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
+#include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/MC/MCAsmBackend.h"
+#include "llvm/MC/MCSection.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 
 namespace llvm {
@@ -33,11 +35,23 @@ class RISCVAsmBackend : public MCAsmBackend {
 
   StringMap<MCSymbol *> VendorSymbols;
 
+  SmallPtrSet<const MCSection *, 8> RelaxEverSections;
+  SmallPtrSet<const MCSection *, 8> RVCEverSections;
+
 public:
   RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
                   const MCTargetOptions &Options);
   ~RISCVAsmBackend() override = default;
 
+  void setRVCEver(const MCSection *Sec) { RVCEverSections.insert(Sec); }
+  bool hasRVCEver(const MCSection *Sec) const {
+    return RVCEverSections.contains(Sec);
+  }
+  void setRelaxEver(const MCSection *Sec) { RelaxEverSections.insert(Sec); }
+  bool hasRelaxEver(const MCSection *Sec) const {
+    return RelaxEverSections.contains(Sec);
+  }
+
   std::optional<bool> evaluateFixup(const MCFragment &, MCFixup &, MCValue &,
                                     uint64_t &) override;
   bool addReloc(const MCFragment &, const MCFixup &, const MCValue &,

llvm/test/MC/RISCV/align-option-norelax-norvc.s

@@ -0,0 +1,34 @@
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax,+c,+m %s -o - | \
+# RUN: llvm-objdump -dr --mattr=+c,+m - | FileCheck %s
+
+        .text
+        .option relax
+        .balign 4
+        .global _start
+        .type _start, @function
+# This R_RISCV_ALIGN for .balign 4
+# CHECK: R_RISCV_ALIGN *ABS*+0x2
+_start:
+        lui a0, %hi(foo)
+        addi a0, a0, %lo(foo)
+	mul a0, a1, a4
+        .option push
+
+        .option norelax
+        .option norvc
+# This R_RISCV_ALIGN for .balign 8, we should emit that even
+# norelax is set, because the code before this point might relax,
+# and size may changed, so that we need to align this again at linker
+# time.
+# Also padding pad should be +6 rather than +4 here, because we have enabled
+# RVC before, and linker may relax instructions to RVC instructions,
+# That will cause 4 byte padding might not be enough to fix the alignment.
+# CHECK: R_RISCV_ALIGN *ABS*+0x6
+        .balign 8
+SHOULD_ALIGN_8_HERE:
+        .word 0x12345678
+
+        .option pop
+
+foo:
+        ret

llvm/test/MC/RISCV/align-option-norelax.s

@@ -0,0 +1,30 @@
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax,+c,+m %s -o - | \
+# RUN: llvm-objdump -dr --mattr=+c,+m - | FileCheck %s
+
+        .text
+        .option relax
+        .balign 4
+        .global _start
+        .type _start, @function
+# This R_RISCV_ALIGN for .balign 4
+# CHECK: R_RISCV_ALIGN *ABS*+0x2
+_start:
+        lui a0, %hi(foo)
+        addi a0, a0, %lo(foo)
+	mul a0, a1, a4
+        .option push
+
+        .option norelax
+# This R_RISCV_ALIGN for .balign 8, we should emit that even
+# norelax is set, because the code before this point might relax,
+# and size may changed, so that we need to align this again at linker
+# time.
+# CHECK: R_RISCV_ALIGN *ABS*+0x6
+        .balign 8
+SHOULD_ALIGN_8_HERE:
+        .word 0x12345678
+
+        .option pop
+
+foo:
+        ret