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[RISCV] Pass sign-extended value to isInt check in expandMul #150211

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Merged
merged 3 commits into from
Jul 25, 2025
Merged

[RISCV] Pass sign-extended value to isInt check in expandMul #150211

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a5a125c
[RISCV] Pass sign-extended value to isInt check in expandMul
svs-quic Jul 23, 2025
f648020
Pre-commit test
svs-quic Jul 24, 2025
4b685d3
Fix again
svs-quic Jul 24, 2025
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -16079,7 +16079,7 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG,
uint64_t MulAmt = CNode->getZExtValue();

// Don't do this if the Xqciac extension is enabled and the MulAmt in simm12.
if (Subtarget.hasVendorXqciac() && isInt<12>(CNode->getSExtValue()))
if (Subtarget.hasVendorXqciac() && isInt<12>(MulAmt))
return SDValue();

const bool HasShlAdd = Subtarget.hasStdExtZba() ||
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24 changes: 24 additions & 0 deletions llvm/test/CodeGen/RISCV/xqciac.ll
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Expand Up @@ -463,3 +463,27 @@ entry:
%add = add nsw i32 %shlc1, %shlc2
ret i32 %add
}

define i32 @testmuliaddnegimm(i32 %a, i32 %b) {
; RV32IM-LABEL: testmuliaddnegimm:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a1, a0, 1
; RV32IM-NEXT: add a0, a1, a0
; RV32IM-NEXT: li a1, 3
; RV32IM-NEXT: sub a0, a1, a0
; RV32IM-NEXT: ret
;
; RV32IMXQCIAC-LABEL: testmuliaddnegimm:
; RV32IMXQCIAC: # %bb.0:
; RV32IMXQCIAC-NEXT: li a1, 3
; RV32IMXQCIAC-NEXT: qc.muliadd a1, a0, -3
; RV32IMXQCIAC-NEXT: mv a0, a1
; RV32IMXQCIAC-NEXT: ret
;
; RV32IZBAMXQCIAC-LABEL: testmuliaddnegimm:
; RV32IZBAMXQCIAC: # %bb.0:
; RV32IZBAMXQCIAC-NEXT: ret
%mul = mul i32 %a, -3
%add = add i32 %mul, 3
ret i32 %add
}