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[RISCV][IA] Rework VL for strided LD/ST optimization [nfc] #150525

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Merged
merged 1 commit into from
Jul 25, 2025
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[RISCV][IA] Rework VL for strided LD/ST optimization [nfc] #150525

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15 changes: 7 additions & 8 deletions llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -224,10 +224,10 @@ bool RISCVTargetLowering::lowerInterleavedLoad(
Value *Stride = ConstantInt::get(XLenTy, Factor * ScalarSizeInBytes);
Value *Offset = ConstantInt::get(XLenTy, Indices[0] * ScalarSizeInBytes);
Value *BasePtr = Builder.CreatePtrAdd(Ptr, Offset);
// Note: Same VL as above, but i32 not xlen due to signature of
// vp.strided.load
VL = Builder.CreateElementCount(Builder.getInt32Ty(),
VTy->getElementCount());
// For rv64, need to truncate i64 to i32 to match signature. As VL is at most
// the number of active lanes (which is bounded by i32) this is safe.
VL = Builder.CreateTrunc(VL, Builder.getInt32Ty());

CallInst *CI =
Builder.CreateIntrinsic(Intrinsic::experimental_vp_strided_load,
{VTy, BasePtr->getType(), Stride->getType()},
Expand Down Expand Up @@ -302,10 +302,9 @@ bool RISCVTargetLowering::lowerInterleavedStore(Instruction *Store,
Value *Stride = ConstantInt::get(XLenTy, Factor * ScalarSizeInBytes);
Value *Offset = ConstantInt::get(XLenTy, Index * ScalarSizeInBytes);
Value *BasePtr = Builder.CreatePtrAdd(Ptr, Offset);
// Note: Same VL as above, but i32 not xlen due to signature of
// vp.strided.store
VL = Builder.CreateElementCount(Builder.getInt32Ty(),
VTy->getElementCount());
// For rv64, need to truncate i64 to i32 to match signature. As VL is at
// most the number of active lanes (which is bounded by i32) this is safe.
VL = Builder.CreateTrunc(VL, Builder.getInt32Ty());

CallInst *CI =
Builder.CreateIntrinsic(Intrinsic::experimental_vp_strided_store,
Expand Down
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