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[RISCV] Merge some of the C_*_HINT instruction into the regular C_* instructions. #150710

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Merged
merged 4 commits into from
Jul 26, 2025
Merged

[RISCV] Merge some of the C_*_HINT instruction into the regular C_* instructions. #150710

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8e214f8
[RISCV] Merge some of the C_*_HINT instruction into the regular C_* i…
topperc Jul 25, 2025
935b05a
fixup! Fix CI failures
topperc Jul 25, 2025
a7e2f42
fixup! clang-format
topperc Jul 26, 2025
8c32e61
fixup! address review comment
topperc Jul 26, 2025
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110 changes: 6 additions & 104 deletions llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -193,21 +193,19 @@ static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, uint32_t RegNo,
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
if (RegNo == 0) {
if (RegNo == 0)
return MCDisassembler::Fail;
}

return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
}

static DecodeStatus
DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address,
const MCDisassembler *Decoder) {
if (RegNo == 2) {
static DecodeStatus DecodeGPRNoX2RegisterClass(MCInst &Inst, uint64_t RegNo,
uint32_t Address,
const MCDisassembler *Decoder) {
if (RegNo == 2)
return MCDisassembler::Fail;
}

return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
}

static DecodeStatus DecodeGPRNoX31RegisterClass(MCInst &Inst, uint32_t RegNo,
Expand Down Expand Up @@ -536,30 +534,6 @@ static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address,
return MCDisassembler::Success;
}

static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder);

static DecodeStatus decodeRVCInstrRdSImm6(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder);

static DecodeStatus decodeRVCInstrRdCLUIImm(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder);

static DecodeStatus
decodeRVCInstrRdRs1UImmLog2XLenNonZero(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder);

static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder);

static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder);

static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
uint64_t Address,
Expand All @@ -579,18 +553,6 @@ static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,

#include "RISCVGenDisassemblerTables.inc"

static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
if (!Check(S, DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(Inst.getOperand(0));
Inst.addOperand(MCOperand::createImm(0));
return S;
}

static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
Expand All @@ -601,66 +563,6 @@ static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
return MCDisassembler::Success;
}

static DecodeStatus decodeRVCInstrRdSImm6(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
Inst.addOperand(MCOperand::createReg(RISCV::X0));
uint32_t Imm =
fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
[[maybe_unused]] DecodeStatus Result =
decodeSImmOperand<6>(Inst, Imm, Address, Decoder);
assert(Result == MCDisassembler::Success && "Invalid immediate");
return MCDisassembler::Success;
}

static DecodeStatus decodeRVCInstrRdCLUIImm(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
Inst.addOperand(MCOperand::createReg(RISCV::X0));
uint32_t Imm =
fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
return decodeCLUIImmOperand(Inst, Imm, Address, Decoder);
}

static DecodeStatus
decodeRVCInstrRdRs1UImmLog2XLenNonZero(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
Inst.addOperand(MCOperand::createReg(RISCV::X0));
Inst.addOperand(Inst.getOperand(0));

uint32_t UImm6 =
fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
return decodeUImmLog2XLenNonZeroOperand(Inst, UImm6, Address, Decoder);
}

static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
if (!Check(S, DecodeGPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder)))
return MCDisassembler::Fail;
return S;
}

static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
DecodeStatus S = MCDisassembler::Success;
uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
if (!Check(S, DecodeGPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(Inst.getOperand(0));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder)))
return MCDisassembler::Fail;
return S;
}

static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -293,7 +293,7 @@ void RISCVAsmPrinter::emitNTLHint(const MachineInstr *MI) {

MCInst Hint;
if (STI->hasStdExtZca())
Hint.setOpcode(RISCV::C_ADD_HINT);
Hint.setOpcode(RISCV::C_ADD);
else
Hint.setOpcode(RISCV::ADD);

Expand Down
70 changes: 11 additions & 59 deletions llvm/lib/Target/RISCV/RISCVInstrInfoC.td
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Original file line number Diff line number Diff line change
Expand Up @@ -402,7 +402,7 @@ def C_NOP : RVInst16CI<0b000, 0b01, (outs), (ins), "c.nop", "">,

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def C_ADDI : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, simm6nonzero:$imm),
(ins GPRNoX0:$rd, simm6:$imm),
"c.addi", "$rd, $imm">,
Sched<[WriteIALU, ReadIALU]> {
let Constraints = "$rd = $rd_wb";
Expand Down Expand Up @@ -430,7 +430,7 @@ def C_ADDIW : RVInst16CI<0b001, 0b01, (outs GPRNoX0:$rd_wb),
}

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def C_LI : RVInst16CI<0b010, 0b01, (outs GPRNoX0:$rd), (ins simm6:$imm),
def C_LI : RVInst16CI<0b010, 0b01, (outs GPR:$rd), (ins simm6:$imm),
"c.li", "$rd, $imm">,
Sched<[WriteIALU]>;

Expand All @@ -449,7 +449,7 @@ def C_ADDI16SP : RVInst16CI<0b011, 0b01, (outs SP:$rd_wb),
}

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def C_LUI : RVInst16CI<0b011, 0b01, (outs GPRNoX0X2:$rd),
def C_LUI : RVInst16CI<0b011, 0b01, (outs GPRNoX2:$rd),
(ins c_lui_imm:$imm),
"c.lui", "$rd, $imm">,
Sched<[WriteIALU]>;
Expand Down Expand Up @@ -497,7 +497,7 @@ def C_BEQZ : Bcz<0b110, "c.beqz">, Sched<[WriteJmp, ReadJmp]>;
def C_BNEZ : Bcz<0b111, "c.bnez">, Sched<[WriteJmp, ReadJmp]>;

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb),
def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb),
(ins GPRNoX0:$rd, uimmlog2xlennonzero:$imm),
"c.slli", "$rd, $imm">,
Sched<[WriteShiftImm, ReadShiftImm]> {
Expand Down Expand Up @@ -544,7 +544,7 @@ def C_JR : RVInst16CR<0b1000, 0b10, (outs), (ins GPRNoX0:$rs1),

let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isMoveReg = 1,
isAsCheapAsAMove = 1 in
def C_MV : RVInst16CR<0b1000, 0b10, (outs GPRNoX0:$rs1), (ins GPRNoX0:$rs2),
def C_MV : RVInst16CR<0b1000, 0b10, (outs GPR:$rs1), (ins GPRNoX0:$rs2),
"c.mv", "$rs1, $rs2">,
Sched<[WriteIALU, ReadIALU]>;

Expand All @@ -557,8 +557,8 @@ def C_JALR : RVInst16CR<0b1001, 0b10, (outs), (ins GPRNoX0:$rs1),
"c.jalr", "$rs1">, Sched<[WriteJalr, ReadJalr]>;

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPRNoX0:$rd),
(ins GPRNoX0:$rs1, GPRNoX0:$rs2),
def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPR:$rd),
(ins GPR:$rs1, GPRNoX0:$rs2),
"c.add", "$rs1, $rs2">,
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
let Constraints = "$rs1 = $rd";
Expand Down Expand Up @@ -616,54 +616,6 @@ def C_NOP_HINT : RVInst16CI<0b000, 0b01, (outs), (ins simm6nonzero:$imm),
let rd = 0;
}

def C_ADDI_HINT_IMM_ZERO : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, immzero:$imm),
"c.addi", "$rd, $imm">,
Sched<[WriteIALU, ReadIALU]> {
let Constraints = "$rd = $rd_wb";
let imm = 0;
let DecoderMethod = "decodeRVCInstrRdRs1ImmZero";
}

def C_LI_HINT : RVInst16CI<0b010, 0b01, (outs GPRX0:$rd), (ins simm6:$imm),
"c.li", "$rd, $imm">,
Sched<[WriteIALU]> {
let Inst{11-7} = 0;
let DecoderMethod = "decodeRVCInstrRdSImm6";
}

def C_LUI_HINT : RVInst16CI<0b011, 0b01, (outs GPRX0:$rd),
(ins c_lui_imm:$imm),
"c.lui", "$rd, $imm">,
Sched<[WriteIALU]> {
let Inst{11-7} = 0;
let DecoderMethod = "decodeRVCInstrRdCLUIImm";
}

def C_MV_HINT : RVInst16CR<0b1000, 0b10, (outs GPRX0:$rs1), (ins GPRNoX0:$rs2),
"c.mv", "$rs1, $rs2">, Sched<[WriteIALU, ReadIALU]> {
let Inst{11-7} = 0;
let DecoderMethod = "decodeRVCInstrRdRs2";
}

def C_ADD_HINT : RVInst16CR<0b1001, 0b10, (outs GPRX0:$rd),
(ins GPRX0:$rs1, GPRNoX0:$rs2),
"c.add", "$rs1, $rs2">,
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
let Constraints = "$rs1 = $rd";
let Inst{11-7} = 0;
let DecoderMethod = "decodeRVCInstrRdRs1Rs2";
}

def C_SLLI_HINT : RVInst16CI<0b000, 0b10, (outs GPRX0:$rd_wb),
(ins GPRX0:$rd, uimmlog2xlennonzero:$imm),
"c.slli", "$rd, $imm">,
Sched<[WriteShiftImm, ReadShiftImm]> {
let Constraints = "$rd = $rd_wb";
let Inst{11-7} = 0;
let DecoderMethod = "decodeRVCInstrRdRs1UImmLog2XLenNonZero";
}

def C_SLLI64_HINT : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb), (ins GPR:$rd),
"c.slli64", "$rd">,
Sched<[WriteShiftImm, ReadShiftImm]> {
Expand Down Expand Up @@ -704,10 +656,10 @@ def : InstAlias<"c.addi x0, $imm", (C_NOP_HINT simm6nonzero:$imm), 0>;
}

let Predicates = [HasStdExtC, HasStdExtZihintntl] in {
def : InstAlias<"c.ntl.p1", (C_ADD_HINT X0, X2)>;
def : InstAlias<"c.ntl.pall", (C_ADD_HINT X0, X3)>;
def : InstAlias<"c.ntl.s1", (C_ADD_HINT X0, X4)>;
def : InstAlias<"c.ntl.all", (C_ADD_HINT X0, X5)>;
def : InstAlias<"c.ntl.p1", (C_ADD X0, X2)>;
def : InstAlias<"c.ntl.pall", (C_ADD X0, X3)>;
def : InstAlias<"c.ntl.s1", (C_ADD X0, X4)>;
def : InstAlias<"c.ntl.all", (C_ADD X0, X5)>;
} // Predicates = [HasStdExtC, HasStdExtZihintntl]

let EmitPriority = 0 in {
Expand Down
5 changes: 5 additions & 0 deletions llvm/lib/Target/RISCV/RISCVRegisterInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -268,6 +268,11 @@ def GPRNoX0 : GPRRegisterClass<(sub GPR, X0)> {
let DiagnosticString = "register must be a GPR excluding zero (x0)";
}

def GPRNoX2 : GPRRegisterClass<(sub GPR, X2)> {
let DiagnosticType = "InvalidRegClassGPRNoX2";
let DiagnosticString = "register must be a GPR excluding sp (x2)";
}

def GPRNoX0X2 : GPRRegisterClass<(sub GPR, X0, X2)> {
let DiagnosticType = "InvalidRegClassGPRNoX0X2";
let DiagnosticString = "register must be a GPR excluding zero (x0) and sp (x2)";
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/MC/RISCV/rv32c-invalid.s
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Expand Up @@ -26,8 +26,8 @@ c.jalr zero # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding zero
c.mv ra, x0 # CHECK: :[[@LINE]]:11: error: register must be a GPR excluding zero (x0)
c.add ra, ra, x0 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction

## GPRNoX0X2
c.lui x2, 4 # CHECK: :[[@LINE]]:7: error: register must be a GPR excluding zero (x0) and sp (x2){{$}}
## GPRNoX2
c.lui x2, 4 # CHECK: :[[@LINE]]:7: error: register must be a GPR excluding sp (x2){{$}}

## SP
c.addi4spn a0, a0, 12 # CHECK: :[[@LINE]]:17: error: register must be sp (x2)
Expand Down
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