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Reserve R9 on armv6 iOS 2.x #150835

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Merged
merged 15 commits into from
Oct 1, 2025
Merged

Reserve R9 on armv6 iOS 2.x #150835

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55f1ff0
Reserve R9 on iOS before 3.0
Un1q32 Jul 27, 2025
bdf113a
Merge branch 'llvm:main' into main
Un1q32 Aug 2, 2025
e1fdb0d
Merge branch 'llvm:main' into main
Un1q32 Aug 17, 2025
1eec424
Merge branch 'llvm:main' into main
Un1q32 Aug 26, 2025
2e74395
add test for iOS 2 ABI
Un1q32 Aug 27, 2025
4f3b835
apply this to armv6 and armv6k
Un1q32 Aug 27, 2025
1cf6018
remove whitespace
Un1q32 Aug 27, 2025
ae62d10
Merge branch 'llvm:main' into main
Un1q32 Sep 3, 2025
04ac545
Merge branch 'main' into main
Un1q32 Sep 6, 2025
085f7ce
Merge branch 'llvm:main' into main
Un1q32 Sep 10, 2025
4253d55
Merge branch 'main' into main
Un1q32 Sep 15, 2025
d4b9797
Merge branch 'main' into main
Un1q32 Sep 22, 2025
82e448e
Merge branch 'llvm:main' into main
Un1q32 Sep 29, 2025
e3e5f50
Update llvm/test/CodeGen/ARM/inline-asm-clobber.ll
Un1q32 Sep 29, 2025
f1e3a21
oh hey does this work?
Un1q32 Sep 29, 2025
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6 changes: 5 additions & 1 deletion llvm/lib/Target/ARM/ARMSubtarget.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -225,7 +225,11 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
(isTargetDarwin() || DM == DenormalMode::getPreserveSign()))
HasNEONForFP = true;

if (isRWPI())
const ARM::ArchKind Arch = ARM::parseArch(TargetTriple.getArchName());
if (isRWPI() ||
(isTargetIOS() &&
(Arch == ARM::ArchKind::ARMV6K || Arch == ARM::ArchKind::ARMV6) &&
TargetTriple.isOSVersionLT(3, 0)))
ReserveR9 = true;

// If MVEVectorCostFactor is still 0 (has not been set to anything else), default it to 2
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7 changes: 7 additions & 0 deletions llvm/test/CodeGen/ARM/inline-asm-clobber.ll
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Expand Up @@ -6,12 +6,19 @@
; RUN: llc <%s -mtriple=arm-none-eabi --frame-pointer=all 2>&1 \
; RUN: | FileCheck %s -check-prefix=NO_FP_ELIM

; RUN: llc <%s -mtriple=armv6k-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOS2
; RUN: llc <%s -mtriple=armv6k-apple-ios3 2>&1 | FileCheck %s -check-prefix=IOS3
; RUN: llc <%s -mtriple=armv7-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOSV7

; CHECK: warning: inline asm clobber list contains reserved registers: SP, PC
; CHECK: warning: inline asm clobber list contains reserved registers: R11
; RWPI: warning: inline asm clobber list contains reserved registers: R9, SP, PC
; RWPI: warning: inline asm clobber list contains reserved registers: R11
; NO_FP_ELIM: warning: inline asm clobber list contains reserved registers: R11, SP, PC
; NO_FP_ELIM: warning: inline asm clobber list contains reserved registers: R11
; IOS2: warning: inline asm clobber list contains reserved registers: R9, SP, PC
; IOS3: warning: inline asm clobber list contains reserved registers: SP, PC
; IOSV7: warning: inline asm clobber list contains reserved registers: SP, PC

define void @foo() nounwind {
call void asm sideeffect "mov r7, #1",
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