AMDGPU: Remove -stress-regalloc arguments from mfma selection tests #150890

arsenm · 2025-07-28T06:54:41Z

I'm not really sure what the point of these was, but they originated
in the base support commit for gfx942 mfma support. These don't impact
the selection at all, so don't belong in this test. These were causing
allocation failure depending on whether or not the AGPR or VGPR form
was used.

The intent of these tests broke at some point; these were supposed to test both selection paths but the agpr and vgpr versions of the test functions were both selecting to the AGPR version. Explicitly disable AGPR usage with the attribute.

I'm not really sure what the point of these was, but they originated in the base support commit for gfx942 mfma support. These don't impact the selection at all, so don't belong in this test. These were causing allocation failure depending on whether or not the AGPR or VGPR form was used.

arsenm · 2025-07-28T06:55:00Z

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llvmbot · 2025-07-28T06:55:17Z

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

I'm not really sure what the point of these was, but they originated
in the base support commit for gfx942 mfma support. These don't impact
the selection at all, so don't belong in this test. These were causing
allocation failure depending on whether or not the AGPR or VGPR form
was used.

Full diff: https://github.com/llvm/llvm-project/pull/150890.diff

2 Files Affected:

(modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll (-4)
(modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll (-123)

diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
index 7d85d3439eed9..beda16c17a5c9 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
@@ -1,13 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck --check-prefixes=GFX942,GFX942-VGPRCD,GFX942-SDAG,GFX942-VGPRCD-SDAG %s
 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck --check-prefixes=GFX942,GFX942-VGPRCD,GFX942-GISEL,GFX942-VGPRCD-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 -stress-regalloc=10 < %s | FileCheck --check-prefixes=GFX942,GFX942-AGPRCD,GFX942-SDAG,GFX942-AGPRCD-SDAG %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx942 -stress-regalloc=10 < %s | FileCheck --check-prefixes=GFX942,GFX942-AGPRCD,GFX942-GISEL,GFX942-AGPRCD-GISEL %s
 
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck --check-prefixes=GFX950,GFX950-VGPRCD,GFX950-SDAG,GFX950-VGPRCD-SDAG %s
 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck --check-prefixes=GFX950,GFX950-VGPRCD,GFX950-GISEL,GFX950-VGPRCD-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 -stress-regalloc=10 < %s | FileCheck --check-prefixes=GFX950,GFX950-AGPRCD,GFX950-SDAG,GFX950-AGPRCD-SDAG %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx950 -stress-regalloc=10 < %s | FileCheck --check-prefixes=GFX950,GFX950-AGPRCD,GFX950-GISEL,GFX950-AGPRCD-GISEL %s
 
 declare <4 x i32> @llvm.amdgcn.mfma.i32.16x16x32.i8(i64, i64, <4 x i32>, i32, i32, i32)
 declare <16 x i32> @llvm.amdgcn.mfma.i32.32x32x16.i8(i64, i64, <16 x i32>, i32, i32, i32)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
index ea9334a6c74d3..31a48de4133ac 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
@@ -1,8 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck --check-prefixes=GFX942,GFX942-SDAG %s
 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck --check-prefixes=GFX942,GFX942-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 -stress-regalloc=10 < %s | FileCheck --check-prefixes=GFX942-STRESS,GFX942-SDAG-STRESS %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx942 -stress-regalloc=10 < %s | FileCheck --check-prefixes=GFX942-STRESS,GFX942-GISEL-STRESS %s
 
 declare <4 x float> @llvm.amdgcn.mfma.f32.16x16x8.xf32(<2 x float>, <2 x float>, <4 x float>, i32, i32, i32)
 declare <16 x float> @llvm.amdgcn.mfma.f32.32x32x4.xf32(<2 x float>, <2 x float>, <16 x float>, i32, i32, i32)
@@ -51,50 +49,6 @@ define amdgpu_kernel void @test_mfma_f32_16x16x8xf32(ptr addrspace(1) %arg) #0 {
 ; GFX942-GISEL-NEXT:    s_nop 5
 ; GFX942-GISEL-NEXT:    global_store_dwordx4 v0, a[0:3], s[6:7]
 ; GFX942-GISEL-NEXT:    s_endpgm
-;
-; GFX942-SDAG-STRESS-LABEL: test_mfma_f32_16x16x8xf32:
-; GFX942-SDAG-STRESS:       ; %bb.0: ; %bb
-; GFX942-SDAG-STRESS-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX942-SDAG-STRESS-NEXT:    v_mov_b32_e32 v0, 1.0
-; GFX942-SDAG-STRESS-NEXT:    v_mov_b32_e32 v1, 2.0
-; GFX942-SDAG-STRESS-NEXT:    v_mov_b32_e32 v2, 0x40400000
-; GFX942-SDAG-STRESS-NEXT:    v_mov_b32_e32 v3, 4.0
-; GFX942-SDAG-STRESS-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX942-SDAG-STRESS-NEXT:    s_load_dwordx4 s[0:3], s[6:7], 0x0
-; GFX942-SDAG-STRESS-NEXT:    v_mov_b32_e32 v4, 0
-; GFX942-SDAG-STRESS-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a0, s0
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a1, s1
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a2, s2
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a3, s3
-; GFX942-SDAG-STRESS-NEXT:    s_nop 1
-; GFX942-SDAG-STRESS-NEXT:    v_mfma_f32_16x16x8_xf32 a[0:3], v[0:1], v[2:3], a[0:3] cbsz:1 abid:2 blgp:3
-; GFX942-SDAG-STRESS-NEXT:    s_nop 6
-; GFX942-SDAG-STRESS-NEXT:    global_store_dwordx4 v4, a[0:3], s[6:7]
-; GFX942-SDAG-STRESS-NEXT:    s_endpgm
-;
-; GFX942-GISEL-STRESS-LABEL: test_mfma_f32_16x16x8xf32:
-; GFX942-GISEL-STRESS:       ; %bb.0: ; %bb
-; GFX942-GISEL-STRESS-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX942-GISEL-STRESS-NEXT:    s_mov_b32 s0, 1.0
-; GFX942-GISEL-STRESS-NEXT:    s_mov_b32 s2, 0x40400000
-; GFX942-GISEL-STRESS-NEXT:    s_mov_b32 s1, 2.0
-; GFX942-GISEL-STRESS-NEXT:    s_mov_b32 s3, 4.0
-; GFX942-GISEL-STRESS-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]
-; GFX942-GISEL-STRESS-NEXT:    v_mov_b64_e32 v[2:3], s[2:3]
-; GFX942-GISEL-STRESS-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX942-GISEL-STRESS-NEXT:    s_load_dwordx4 s[0:3], s[6:7], 0x0
-; GFX942-GISEL-STRESS-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a0, s0
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a1, s1
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a2, s2
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a3, s3
-; GFX942-GISEL-STRESS-NEXT:    s_nop 1
-; GFX942-GISEL-STRESS-NEXT:    v_mfma_f32_16x16x8_xf32 a[0:3], v[0:1], v[2:3], a[0:3] cbsz:1 abid:2 blgp:3
-; GFX942-GISEL-STRESS-NEXT:    v_mov_b32_e32 v0, 0
-; GFX942-GISEL-STRESS-NEXT:    s_nop 5
-; GFX942-GISEL-STRESS-NEXT:    global_store_dwordx4 v0, a[0:3], s[6:7]
-; GFX942-GISEL-STRESS-NEXT:    s_endpgm
 bb:
   %in.1 = load <4 x float>, ptr addrspace(1) %arg
   %mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.16x16x8.xf32(<2 x float> <float 1.0, float 2.0>, <2 x float> <float 3.0, float 4.0>, <4 x float> %in.1, i32 1, i32 2, i32 3)
@@ -178,82 +132,6 @@ define amdgpu_kernel void @test_mfma_f32_32x32x4xf32(ptr addrspace(1) %arg) #0 {
 ; GFX942-GISEL-NEXT:    global_store_dwordx4 v0, a[8:11], s[16:17] offset:32
 ; GFX942-GISEL-NEXT:    global_store_dwordx4 v0, a[12:15], s[16:17] offset:48
 ; GFX942-GISEL-NEXT:    s_endpgm
-;
-; GFX942-SDAG-STRESS-LABEL: test_mfma_f32_32x32x4xf32:
-; GFX942-SDAG-STRESS:       ; %bb.0: ; %bb
-; GFX942-SDAG-STRESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x24
-; GFX942-SDAG-STRESS-NEXT:    v_mov_b32_e32 v0, 1.0
-; GFX942-SDAG-STRESS-NEXT:    v_mov_b32_e32 v1, 2.0
-; GFX942-SDAG-STRESS-NEXT:    v_mov_b32_e32 v2, 0x40400000
-; GFX942-SDAG-STRESS-NEXT:    v_mov_b32_e32 v3, 4.0
-; GFX942-SDAG-STRESS-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX942-SDAG-STRESS-NEXT:    s_load_dwordx16 s[0:15], s[16:17], 0x0
-; GFX942-SDAG-STRESS-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a0, s0
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a1, s1
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a2, s2
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a3, s3
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a4, s4
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a5, s5
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a6, s6
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a7, s7
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a8, s8
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a9, s9
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a10, s10
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a11, s11
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a12, s12
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a13, s13
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a14, s14
-; GFX942-SDAG-STRESS-NEXT:    v_accvgpr_write_b32 a15, s15
-; GFX942-SDAG-STRESS-NEXT:    s_nop 1
-; GFX942-SDAG-STRESS-NEXT:    v_mfma_f32_32x32x4_xf32 a[0:15], v[0:1], v[2:3], a[0:15] cbsz:1 abid:2 blgp:3
-; GFX942-SDAG-STRESS-NEXT:    v_mov_b32_e32 v0, 0
-; GFX942-SDAG-STRESS-NEXT:    s_nop 7
-; GFX942-SDAG-STRESS-NEXT:    s_nop 1
-; GFX942-SDAG-STRESS-NEXT:    global_store_dwordx4 v0, a[12:15], s[16:17] offset:48
-; GFX942-SDAG-STRESS-NEXT:    global_store_dwordx4 v0, a[8:11], s[16:17] offset:32
-; GFX942-SDAG-STRESS-NEXT:    global_store_dwordx4 v0, a[4:7], s[16:17] offset:16
-; GFX942-SDAG-STRESS-NEXT:    global_store_dwordx4 v0, a[0:3], s[16:17]
-; GFX942-SDAG-STRESS-NEXT:    s_endpgm
-;
-; GFX942-GISEL-STRESS-LABEL: test_mfma_f32_32x32x4xf32:
-; GFX942-GISEL-STRESS:       ; %bb.0: ; %bb
-; GFX942-GISEL-STRESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x24
-; GFX942-GISEL-STRESS-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX942-GISEL-STRESS-NEXT:    s_load_dwordx16 s[0:15], s[16:17], 0x0
-; GFX942-GISEL-STRESS-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a0, s0
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a1, s1
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a2, s2
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a3, s3
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a4, s4
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a5, s5
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a6, s6
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a7, s7
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a8, s8
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a9, s9
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a10, s10
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a11, s11
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a12, s12
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a13, s13
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a14, s14
-; GFX942-GISEL-STRESS-NEXT:    v_accvgpr_write_b32 a15, s15
-; GFX942-GISEL-STRESS-NEXT:    s_mov_b32 s0, 1.0
-; GFX942-GISEL-STRESS-NEXT:    s_mov_b32 s1, 2.0
-; GFX942-GISEL-STRESS-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]
-; GFX942-GISEL-STRESS-NEXT:    s_mov_b32 s0, 0x40400000
-; GFX942-GISEL-STRESS-NEXT:    s_mov_b32 s1, 4.0
-; GFX942-GISEL-STRESS-NEXT:    v_mov_b64_e32 v[2:3], s[0:1]
-; GFX942-GISEL-STRESS-NEXT:    s_nop 1
-; GFX942-GISEL-STRESS-NEXT:    v_mfma_f32_32x32x4_xf32 a[0:15], v[0:1], v[2:3], a[0:15] cbsz:1 abid:2 blgp:3
-; GFX942-GISEL-STRESS-NEXT:    v_mov_b32_e32 v0, 0
-; GFX942-GISEL-STRESS-NEXT:    s_nop 7
-; GFX942-GISEL-STRESS-NEXT:    s_nop 1
-; GFX942-GISEL-STRESS-NEXT:    global_store_dwordx4 v0, a[0:3], s[16:17]
-; GFX942-GISEL-STRESS-NEXT:    global_store_dwordx4 v0, a[4:7], s[16:17] offset:16
-; GFX942-GISEL-STRESS-NEXT:    global_store_dwordx4 v0, a[8:11], s[16:17] offset:32
-; GFX942-GISEL-STRESS-NEXT:    global_store_dwordx4 v0, a[12:15], s[16:17] offset:48
-; GFX942-GISEL-STRESS-NEXT:    s_endpgm
 bb:
   %in.1 = load <16 x float>, ptr addrspace(1) %arg
   %mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.32x32x4.xf32(<2 x float> <float 1.0, float 2.0>, <2 x float> <float 3.0, float 4.0>, <16 x float> %in.1, i32 1, i32 2, i32 3)
@@ -264,4 +142,3 @@ bb:
 attributes #0 = { "amdgpu-flat-work-group-size"="1,256" }
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; GFX942: {{.*}}
-; GFX942-STRESS: {{.*}}

shiltian

There are many internal tickets about crashes exposed by using this option, not for MFMA though. That might be orthogonal to this PR.

arsenm added 2 commits July 28, 2025 13:46

arsenm added the backend:AMDGPU label Jul 28, 2025 — with Graphite App

arsenm mentioned this pull request Jul 28, 2025

AMDGPU: Disable AGPR allocation in VGPR MFMA tests #150873

Merged

arsenm requested a review from rampitec July 28, 2025 06:55

arsenm mentioned this pull request Jul 28, 2025

AMDGPU: Test VGPR and AGPR case for xf32 mfmas #150891

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arsenm marked this pull request as ready for review July 28, 2025 06:55

Base automatically changed from users/arsenm/amdgpu/disable-agpr-usage-vgpr-mfma-select-tests to main July 28, 2025 15:26

shiltian approved these changes Jul 28, 2025

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arsenm merged commit a496a98 into main Jul 28, 2025
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arsenm deleted the users/arsenm/amdgpu/remove-stress-regalloc-10-runlines-mfma-tests branch July 28, 2025 15:30

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AMDGPU: Remove -stress-regalloc arguments from mfma selection tests #150890

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