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[NFC][AMDGPU] Move cmp+select arguments optimization to SIISelLowering. #150929

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Merged
merged 2 commits into from
Jul 28, 2025
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[NFC][AMDGPU] Move cmp+select arguments optimization to SIISelLowering. #150929

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03b089b
[NFC][AMDGPU] Move cmp+select arguments optimization to SIISelLowering.
dfukalov Jul 28, 2025
55d76f6
Fixed clang-format.
dfukalov Jul 28, 2025
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83 changes: 0 additions & 83 deletions llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4846,94 +4846,11 @@ AMDGPUTargetLowering::foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
return SDValue();
}

// Detect when CMP and SELECT use the same constant and fold them to avoid
// loading the constant twice. Specifically handles patterns like:
// %cmp = icmp eq i32 %val, 4242
// %sel = select i1 %cmp, i32 4242, i32 %other
// It can be optimized to reuse %val instead of 4242 in select.
static SDValue
foldCmpSelectWithSharedConstant(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
const AMDGPUSubtarget *ST) {
SDValue Cond = N->getOperand(0);
SDValue TrueVal = N->getOperand(1);
SDValue FalseVal = N->getOperand(2);

// Check if condition is a comparison.
if (Cond.getOpcode() != ISD::SETCC)
return SDValue();

SDValue LHS = Cond.getOperand(0);
SDValue RHS = Cond.getOperand(1);
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();

bool isFloatingPoint = LHS.getValueType().isFloatingPoint();
bool isInteger = LHS.getValueType().isInteger();

// Handle simple floating-point and integer types only.
if (!isFloatingPoint && !isInteger)
return SDValue();

bool isEquality = CC == (isFloatingPoint ? ISD::SETOEQ : ISD::SETEQ);
bool isNonEquality = CC == (isFloatingPoint ? ISD::SETONE : ISD::SETNE);
if (!isEquality && !isNonEquality)
return SDValue();

SDValue ArgVal, ConstVal;
if ((isFloatingPoint && isa<ConstantFPSDNode>(RHS)) ||
(isInteger && isa<ConstantSDNode>(RHS))) {
ConstVal = RHS;
ArgVal = LHS;
} else if ((isFloatingPoint && isa<ConstantFPSDNode>(LHS)) ||
(isInteger && isa<ConstantSDNode>(LHS))) {
ConstVal = LHS;
ArgVal = RHS;
} else {
return SDValue();
}

// Check if constant should not be optimized - early return if not.
if (isFloatingPoint) {
const APFloat &Val = cast<ConstantFPSDNode>(ConstVal)->getValueAPF();
const GCNSubtarget *GCNST = static_cast<const GCNSubtarget *>(ST);

// Only optimize normal floating-point values (finite, non-zero, and
// non-subnormal as per IEEE 754), skip optimization for inlinable
// floating-point constants.
if (!Val.isNormal() || GCNST->getInstrInfo()->isInlineConstant(Val))
return SDValue();
} else {
int64_t IntVal = cast<ConstantSDNode>(ConstVal)->getSExtValue();

// Skip optimization for inlinable integer immediates.
// Inlinable immediates include: -16 to 64 (inclusive).
if (IntVal >= -16 && IntVal <= 64)
return SDValue();
}

// For equality and non-equality comparisons, patterns:
// select (setcc x, const), const, y -> select (setcc x, const), x, y
// select (setccinv x, const), y, const -> select (setccinv x, const), y, x
if (!(isEquality && TrueVal == ConstVal) &&
!(isNonEquality && FalseVal == ConstVal))
return SDValue();

SDValue SelectLHS = (isEquality && TrueVal == ConstVal) ? ArgVal : TrueVal;
SDValue SelectRHS =
(isNonEquality && FalseVal == ConstVal) ? ArgVal : FalseVal;
return DCI.DAG.getNode(ISD::SELECT, SDLoc(N), N->getValueType(0), Cond,
SelectLHS, SelectRHS);
}

SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
if (SDValue Folded = foldFreeOpFromSelect(DCI, SDValue(N, 0)))
return Folded;

// Try to fold CMP + SELECT patterns with shared constants (both FP and
// integer).
if (SDValue Folded = foldCmpSelectWithSharedConstant(N, DCI, Subtarget))
return Folded;

SDValue Cond = N->getOperand(0);
if (Cond.getOpcode() != ISD::SETCC)
return SDValue();
Expand Down
76 changes: 76 additions & 0 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -15896,6 +15896,78 @@ SDValue SITargetLowering::performClampCombine(SDNode *N,
return SDValue(CSrc, 0);
}

SDValue SITargetLowering::performSelectCombine(SDNode *N,
DAGCombinerInfo &DCI) const {

// Try to fold CMP + SELECT patterns with shared constants (both FP and
// integer).
// Detect when CMP and SELECT use the same constant and fold them to avoid
// loading the constant twice. Specifically handles patterns like:
// %cmp = icmp eq i32 %val, 4242
// %sel = select i1 %cmp, i32 4242, i32 %other
// It can be optimized to reuse %val instead of 4242 in select.
SDValue Cond = N->getOperand(0);
SDValue TrueVal = N->getOperand(1);
SDValue FalseVal = N->getOperand(2);

// Check if condition is a comparison.
if (Cond.getOpcode() != ISD::SETCC)
return SDValue();

SDValue LHS = Cond.getOperand(0);
SDValue RHS = Cond.getOperand(1);
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();

bool isFloatingPoint = LHS.getValueType().isFloatingPoint();
bool isInteger = LHS.getValueType().isInteger();

// Handle simple floating-point and integer types only.
if (!isFloatingPoint && !isInteger)
return SDValue();

bool isEquality = CC == (isFloatingPoint ? ISD::SETOEQ : ISD::SETEQ);
bool isNonEquality = CC == (isFloatingPoint ? ISD::SETONE : ISD::SETNE);
if (!isEquality && !isNonEquality)
return SDValue();

SDValue ArgVal, ConstVal;
if ((isFloatingPoint && isa<ConstantFPSDNode>(RHS)) ||
(isInteger && isa<ConstantSDNode>(RHS))) {
ConstVal = RHS;
ArgVal = LHS;
} else if ((isFloatingPoint && isa<ConstantFPSDNode>(LHS)) ||
(isInteger && isa<ConstantSDNode>(LHS))) {
ConstVal = LHS;
ArgVal = RHS;
} else {
return SDValue();
}

// Skip optimization for inlinable immediates.
if (isFloatingPoint) {
const APFloat &Val = cast<ConstantFPSDNode>(ConstVal)->getValueAPF();
if (!Val.isNormal() || Subtarget->getInstrInfo()->isInlineConstant(Val))
return SDValue();
} else {
if (AMDGPU::isInlinableIntLiteral(
cast<ConstantSDNode>(ConstVal)->getSExtValue()))
return SDValue();
Comment on lines +15952 to +15954
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@arsenm arsenm Jul 28, 2025

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Follow up should just use the isInlineConstant utility

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@dfukalov dfukalov Jul 28, 2025 •
edited
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Yes, but it asserts on i8 type. And for this instruction it seems more "straightforward" to use AMDGPU::isInlinableIntLiteral for integer types.

}

// For equality and non-equality comparisons, patterns:
// select (setcc x, const), const, y -> select (setcc x, const), x, y
// select (setccinv x, const), y, const -> select (setccinv x, const), y, x
if (!(isEquality && TrueVal == ConstVal) &&
!(isNonEquality && FalseVal == ConstVal))
return SDValue();

SDValue SelectLHS = (isEquality && TrueVal == ConstVal) ? ArgVal : TrueVal;
SDValue SelectRHS =
(isNonEquality && FalseVal == ConstVal) ? ArgVal : FalseVal;
return DCI.DAG.getNode(ISD::SELECT, SDLoc(N), N->getValueType(0), Cond,
SelectLHS, SelectRHS);
}

SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
switch (N->getOpcode()) {
Expand Down Expand Up @@ -15944,6 +16016,10 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
return performFMulCombine(N, DCI);
case ISD::SETCC:
return performSetCCCombine(N, DCI);
case ISD::SELECT:
if (auto Res = performSelectCombine(N, DCI))
return Res;
break;
case ISD::FMAXNUM:
case ISD::FMINNUM:
case ISD::FMAXNUM_IEEE:
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SIISelLowering.h
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Expand Up @@ -211,6 +211,7 @@ class SITargetLowering final : public AMDGPUTargetLowering {
SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performFPRoundCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;

SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
unsigned getFusedOpcode(const SelectionDAG &DAG,
Expand Down