Skip to content

[AArch64] Use CNEG for absolute difference patterns. #151177

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
rj-jesus merged 2 commits into from
Jul 30, 2025
Merged

[AArch64] Use CNEG for absolute difference patterns. #151177

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
4f71915
[AArch64] Use CNEG for absolute difference patterns.
rj-jesus Jul 28, 2025
7096397
Type comments properly.
rj-jesus Jul 30, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
16 changes: 16 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11386,6 +11386,22 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(
return DAG.getNode(ISD::AND, DL, VT, LHS, Shift);
}

// Canonicalise absolute difference patterns:
// select_cc lhs, rhs, sub(lhs, rhs), sub(rhs, lhs), cc ->
// select_cc lhs, rhs, sub(lhs, rhs), neg(sub(lhs, rhs)), cc
//
// select_cc lhs, rhs, sub(rhs, lhs), sub(lhs, rhs), cc ->
// select_cc lhs, rhs, neg(sub(lhs, rhs)), sub(lhs, rhs), cc
// The second forms can be matched into subs+cneg.
if (TVal.getOpcode() == ISD::SUB && FVal.getOpcode() == ISD::SUB) {
if (TVal.getOperand(0) == LHS && TVal.getOperand(1) == RHS &&
FVal.getOperand(0) == RHS && FVal.getOperand(1) == LHS)
FVal = DAG.getNegative(TVal, DL, TVal.getValueType());
else if (TVal.getOperand(0) == RHS && TVal.getOperand(1) == LHS &&
FVal.getOperand(0) == LHS && FVal.getOperand(1) == RHS)
TVal = DAG.getNegative(FVal, DL, FVal.getValueType());
}

unsigned Opcode = AArch64ISD::CSEL;

// If both the TVal and the FVal are constants, see if we can swap them in
Expand Down
46 changes: 16 additions & 30 deletions llvm/test/CodeGen/AArch64/abds-neg.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -77,10 +77,8 @@ define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i16_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: sub w9, w1, w8
; CHECK-NEXT: subs w8, w8, w1
; CHECK-NEXT: csel w8, w8, w9, gt
; CHECK-NEXT: neg w0, w8
; CHECK-NEXT: subs w8, w1, w8
; CHECK-NEXT: cneg w0, w8, ge
; CHECK-NEXT: ret
%aext = sext i16 %a to i64
%bext = sext i32 %b to i64
Expand Down Expand Up @@ -111,10 +109,8 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: subs w9, w0, w1
; CHECK-NEXT: csel w8, w9, w8, gt
; CHECK-NEXT: neg w0, w8
; CHECK-NEXT: subs w8, w1, w0
; CHECK-NEXT: cneg w0, w8, ge
; CHECK-NEXT: ret
%aext = sext i32 %a to i64
%bext = sext i32 %b to i64
Expand All @@ -129,10 +125,8 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i32_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w1
; CHECK-NEXT: sub w9, w8, w0
; CHECK-NEXT: subs w8, w0, w8
; CHECK-NEXT: csel w8, w8, w9, gt
; CHECK-NEXT: neg w0, w8
; CHECK-NEXT: subs w8, w8, w0
; CHECK-NEXT: cneg w0, w8, ge
; CHECK-NEXT: ret
%aext = sext i32 %a to i64
%bext = sext i16 %b to i64
Expand All @@ -146,10 +140,8 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i32_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: subs w9, w0, w1
; CHECK-NEXT: csel w8, w9, w8, gt
; CHECK-NEXT: neg w0, w8
; CHECK-NEXT: subs w8, w1, w0
; CHECK-NEXT: cneg w0, w8, ge
; CHECK-NEXT: ret
%aext = sext i32 %a to i64
%bext = sext i32 %b to i64
Expand All @@ -163,10 +155,8 @@ define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_ext_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: subs x9, x0, x1
; CHECK-NEXT: csel x8, x9, x8, gt
; CHECK-NEXT: neg x0, x8
; CHECK-NEXT: subs x8, x1, x0
; CHECK-NEXT: cneg x0, x8, ge
; CHECK-NEXT: ret
%aext = sext i64 %a to i128
%bext = sext i64 %b to i128
Expand All @@ -180,10 +170,8 @@ define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_ext_i64_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: subs x9, x0, x1
; CHECK-NEXT: csel x8, x9, x8, gt
; CHECK-NEXT: neg x0, x8
; CHECK-NEXT: subs x8, x1, x0
; CHECK-NEXT: cneg x0, x8, ge
; CHECK-NEXT: ret
%aext = sext i64 %a to i128
%bext = sext i64 %b to i128
Expand Down Expand Up @@ -359,9 +347,8 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_cmp_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: subs w9, w0, w1
; CHECK-NEXT: csel w0, w8, w9, ge
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w0, w8, ge
; CHECK-NEXT: ret
%cmp = icmp sge i32 %a, %b
%ab = sub i32 %a, %b
Expand All @@ -373,9 +360,8 @@ define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_cmp_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: subs x9, x0, x1
; CHECK-NEXT: csel x0, x9, x8, lt
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, ge
; CHECK-NEXT: ret
%cmp = icmp slt i64 %a, %b
%ab = sub i64 %a, %b
Expand Down
56 changes: 22 additions & 34 deletions llvm/test/CodeGen/AArch64/abds.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -73,9 +73,8 @@ define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i16_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: sub w9, w1, w8
; CHECK-NEXT: subs w8, w8, w1
; CHECK-NEXT: csel w0, w8, w9, gt
; CHECK-NEXT: cneg w0, w8, le
; CHECK-NEXT: ret
%aext = sext i16 %a to i64
%bext = sext i32 %b to i64
Expand Down Expand Up @@ -104,9 +103,8 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: subs w9, w0, w1
; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w0, w8, le
; CHECK-NEXT: ret
%aext = sext i32 %a to i64
%bext = sext i32 %b to i64
Expand All @@ -120,9 +118,8 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i32_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w1
; CHECK-NEXT: sub w9, w8, w0
; CHECK-NEXT: subs w8, w0, w8
; CHECK-NEXT: csel w0, w8, w9, gt
; CHECK-NEXT: cneg w0, w8, le
; CHECK-NEXT: ret
%aext = sext i32 %a to i64
%bext = sext i16 %b to i64
Expand All @@ -135,9 +132,8 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i32_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: subs w9, w0, w1
; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w0, w8, le
; CHECK-NEXT: ret
%aext = sext i32 %a to i64
%bext = sext i32 %b to i64
Expand All @@ -150,9 +146,8 @@ define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_ext_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: subs x9, x0, x1
; CHECK-NEXT: csel x0, x9, x8, gt
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, le
; CHECK-NEXT: ret
%aext = sext i64 %a to i128
%bext = sext i64 %b to i128
Expand All @@ -165,9 +160,8 @@ define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_ext_i64_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: subs x9, x0, x1
; CHECK-NEXT: csel x0, x9, x8, gt
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, le
; CHECK-NEXT: ret
%aext = sext i64 %a to i128
%bext = sext i64 %b to i128
Expand Down Expand Up @@ -248,9 +242,8 @@ define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_minmax_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: subs w9, w0, w1
; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w0, w8, le
; CHECK-NEXT: ret
%min = call i32 @llvm.smin.i32(i32 %a, i32 %b)
%max = call i32 @llvm.smax.i32(i32 %a, i32 %b)
Expand All @@ -261,9 +254,8 @@ define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_minmax_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: subs x9, x0, x1
; CHECK-NEXT: csel x0, x9, x8, gt
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, le
; CHECK-NEXT: ret
%min = call i64 @llvm.smin.i64(i64 %a, i64 %b)
%max = call i64 @llvm.smax.i64(i64 %a, i64 %b)
Expand Down Expand Up @@ -324,9 +316,8 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_cmp_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: subs w9, w0, w1
; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w0, w8, le
; CHECK-NEXT: ret
%cmp = icmp slt i32 %a, %b
%ab = sub i32 %a, %b
Expand All @@ -338,9 +329,8 @@ define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_cmp_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: subs x9, x0, x1
; CHECK-NEXT: csel x0, x9, x8, gt
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, le
; CHECK-NEXT: ret
%cmp = icmp sge i64 %a, %b
%ab = sub i64 %a, %b
Expand Down Expand Up @@ -572,9 +562,8 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_select_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: subs w9, w0, w1
; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w0, w8, le
; CHECK-NEXT: ret
%cmp = icmp sgt i32 %a, %b
%ab = select i1 %cmp, i32 %a, i32 %b
Expand All @@ -586,9 +575,8 @@ define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {
define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_select_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: subs x9, x0, x1
; CHECK-NEXT: csel x0, x9, x8, gt
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, le
; CHECK-NEXT: ret
%cmp = icmp sge i64 %a, %b
%ab = select i1 %cmp, i64 %a, i64 %b
Expand Down
46 changes: 16 additions & 30 deletions llvm/test/CodeGen/AArch64/abdu-neg.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -77,10 +77,8 @@ define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i16_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: sub w9, w1, w8
; CHECK-NEXT: subs w8, w8, w1
; CHECK-NEXT: csel w8, w8, w9, hi
; CHECK-NEXT: neg w0, w8
; CHECK-NEXT: subs w8, w1, w8
; CHECK-NEXT: cneg w0, w8, hs
; CHECK-NEXT: ret
%aext = zext i16 %a to i64
%bext = zext i32 %b to i64
Expand Down Expand Up @@ -111,10 +109,8 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: subs w9, w0, w1
; CHECK-NEXT: csel w8, w9, w8, hi
; CHECK-NEXT: neg w0, w8
; CHECK-NEXT: subs w8, w1, w0
; CHECK-NEXT: cneg w0, w8, hs
; CHECK-NEXT: ret
%aext = zext i32 %a to i64
%bext = zext i32 %b to i64
Expand All @@ -129,10 +125,8 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i32_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w1, #0xffff
; CHECK-NEXT: sub w9, w8, w0
; CHECK-NEXT: subs w8, w0, w8
; CHECK-NEXT: csel w8, w8, w9, hi
; CHECK-NEXT: neg w0, w8
; CHECK-NEXT: subs w8, w8, w0
; CHECK-NEXT: cneg w0, w8, hs
; CHECK-NEXT: ret
%aext = zext i32 %a to i64
%bext = zext i16 %b to i64
Expand All @@ -146,10 +140,8 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i32_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: subs w9, w0, w1
; CHECK-NEXT: csel w8, w9, w8, hi
; CHECK-NEXT: neg w0, w8
; CHECK-NEXT: subs w8, w1, w0
; CHECK-NEXT: cneg w0, w8, hs
; CHECK-NEXT: ret
%aext = zext i32 %a to i64
%bext = zext i32 %b to i64
Expand All @@ -163,10 +155,8 @@ define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_ext_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: subs x9, x0, x1
; CHECK-NEXT: csel x8, x9, x8, hi
; CHECK-NEXT: neg x0, x8
; CHECK-NEXT: subs x8, x1, x0
; CHECK-NEXT: cneg x0, x8, hs
; CHECK-NEXT: ret
%aext = zext i64 %a to i128
%bext = zext i64 %b to i128
Expand All @@ -180,10 +170,8 @@ define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_ext_i64_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: subs x9, x0, x1
; CHECK-NEXT: csel x8, x9, x8, hi
; CHECK-NEXT: neg x0, x8
; CHECK-NEXT: subs x8, x1, x0
; CHECK-NEXT: cneg x0, x8, hs
; CHECK-NEXT: ret
%aext = zext i64 %a to i128
%bext = zext i64 %b to i128
Expand Down Expand Up @@ -363,9 +351,8 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_cmp_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: subs w9, w0, w1
; CHECK-NEXT: csel w0, w8, w9, hs
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w0, w8, hs
; CHECK-NEXT: ret
%cmp = icmp uge i32 %a, %b
%ab = sub i32 %a, %b
Expand All @@ -377,9 +364,8 @@ define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_cmp_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: subs x9, x0, x1
; CHECK-NEXT: csel x0, x9, x8, lo
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, hs
; CHECK-NEXT: ret
%cmp = icmp ult i64 %a, %b
%ab = sub i64 %a, %b
Expand Down
Loading