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[MLIR] Define memory effects for memref.prefetch operation #151261

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Merged
merged 16 commits into from
Oct 8, 2025
Merged

[MLIR] Define memory effects for memref.prefetch operation #151261

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7078f7d
add MemWrite side effect to memref.prefetch
AlexandreEichenberger Jul 30, 2025
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update
AlexandreEichenberger Jul 30, 2025
3a7212a
added memref.prefetch MemWrite side effect
AlexandreEichenberger Jul 30, 2025
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Merge branch 'main' into memref-prefetch-side-effect
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Merge branch 'main' into memref-prefetch-side-effect
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Merge branch 'main' into memref-prefetch-side-effect
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Merge branch 'main' into memref-prefetch-side-effect
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Merge branch 'main' into memref-prefetch-side-effect
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6 changes: 5 additions & 1 deletion mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
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Expand Up @@ -1351,7 +1351,11 @@ def MemRef_PrefetchOp : MemRef_Op<"prefetch"> {
instruction cache.
}];

let arguments = (ins AnyMemRef:$memref, Variadic<Index>:$indices,
// The memref argument is labeled with a MemWrite side effect to enforce a
// relative ordering of the prefetch and other memory operations targeting
// that memory stream.
let arguments = (ins Arg<AnyMemRef, "prefetch address", [MemWrite]> :$memref,
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Why do you need to "write to the buffer" semantically here?
(it's worth a comment, as this may not be intuitive!)

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Good suggestion, will add a comment. It's basically to ensure that dead-code analysis does not remove the operation. It is inline with making that operation a "volatile" so that it remains in place with respect to the other load/store of the prefetched data.

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It shouldn't be removing the operation if it doesn't declare any side effects at all though, and conservatively assume it has all possible side effects. It feels like there's a bug somewhere

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@ftynse I believe the source of the problem is that without side-effects defined, the buffer allocation will fail:

"ops with unknown memory side effects are not supported"

So we need to add side effects, and the part about

It's basically to ensure that dead-code analysis does not remove the operation

is only an answer to "why write and not just read".

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An alternative design here, more SSA-friendly, would be for the op to be side-effect free and return a token to be consumed later by some load operation.

Variadic<Index>:$indices,
BoolAttr:$isWrite,
ConfinedAttr<I32Attr, [IntMinValue<0>,
IntMaxValue<3>]>:$localityHint,
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10 changes: 9 additions & 1 deletion mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir
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Expand Up @@ -17,4 +17,12 @@ func.func @func_with_assert(%arg0: index, %arg1: index) {
func.func @func_with_assume_alignment(%arg0: memref<128xi8>) {
%0 = memref.assume_alignment %arg0, 64 : memref<128xi8>
return
}
}

// CHECK-LABEL: func @func_with_prefetch(
// CHECK: memref.prefetch %arg0[%c0, %c0], read, locality<1>, data : memref<4x8xf32>
func.func @func_with_prefetch(%arg0: memref<4x8xf32>) {
%c0 = arith.constant 0 : index
memref.prefetch %arg0[%c0, %c0], read, locality<1>, data : memref<4x8xf32>
return
}