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[AMDGPU] Extending wave reduction intrinsics for i64 types - 3 #151310

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Merged
merged 12 commits into from
Sep 10, 2025
Merged

[AMDGPU] Extending wave reduction intrinsics for i64 types - 3 #151310

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5fa5392
[AMDGPU] Extending wave reduction intrinsics for `i64` types - 1
easyonaadit Jul 19, 2025
cb7ca6e
Addressing Review Comments
easyonaadit Aug 13, 2025
11c9ebc
Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.
easyonaadit Aug 20, 2025
82095ac
[AMDGPU] Extending wave reduction intrinsics for `i64` types - 2
easyonaadit Jul 19, 2025
bc4afc9
Marking dead scc
easyonaadit Aug 13, 2025
634c7e1
Checking for targets with native 64-bit `add`/`sub` support
easyonaadit Aug 20, 2025
e1760a2
[AMDGPU] Extending wave reduction intrinsics for `i64` types - 3
easyonaadit Jul 19, 2025
67819a1
Removing Redundant Instructions
easyonaadit Jul 31, 2025
4565c04
Removing `break` before `else`
easyonaadit Aug 7, 2025
84a7b6a
Running Clang Format
easyonaadit Aug 7, 2025
5dc17b1
Directly checking for S_XOR_B32
easyonaadit Aug 13, 2025
ac6e7ce
Code Formating
easyonaadit Aug 13, 2025
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69 changes: 61 additions & 8 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5356,7 +5356,11 @@ static uint64_t getIdentityValueFor64BitWaveReduction(unsigned Opc) {
return std::numeric_limits<int64_t>::min();
case AMDGPU::S_ADD_U64_PSEUDO:
case AMDGPU::S_SUB_U64_PSEUDO:
case AMDGPU::S_OR_B64:
case AMDGPU::S_XOR_B64:
return std::numeric_limits<uint64_t>::min();
case AMDGPU::S_AND_B64:
return std::numeric_limits<uint64_t>::max();
default:
llvm_unreachable(
"Unexpected opcode in getIdentityValueFor64BitWaveReduction");
Expand Down Expand Up @@ -5398,16 +5402,19 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
RetBB = &BB;
break;
}
case AMDGPU::V_CMP_LT_U64_e64: // umin
case AMDGPU::V_CMP_LT_I64_e64: // min
case AMDGPU::V_CMP_GT_U64_e64: // umax
case AMDGPU::V_CMP_GT_I64_e64: { // max
case AMDGPU::V_CMP_LT_U64_e64: // umin
case AMDGPU::V_CMP_LT_I64_e64: // min
case AMDGPU::V_CMP_GT_U64_e64: // umax
case AMDGPU::V_CMP_GT_I64_e64: // max
case AMDGPU::S_AND_B64:
case AMDGPU::S_OR_B64: {
// Idempotent operations.
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B64), DstReg).addReg(SrcReg);
RetBB = &BB;
break;
}
case AMDGPU::S_XOR_B32:
case AMDGPU::S_XOR_B64:
case AMDGPU::S_ADD_I32:
case AMDGPU::S_ADD_U64_PSEUDO:
case AMDGPU::S_SUB_I32:
Expand All @@ -5431,7 +5438,8 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
.addReg(ExecMask);

switch (Opc) {
case AMDGPU::S_XOR_B32: {
case AMDGPU::S_XOR_B32:
case AMDGPU::S_XOR_B64: {
// Performing an XOR operation on a uniform value
// depends on the parity of the number of active lanes.
// For even parity, the result will be 0, for odd
Expand All @@ -5443,9 +5451,39 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
.addReg(NewAccumulator->getOperand(0).getReg())
.addImm(1)
.setOperandDead(3); // Dead scc
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), DstReg)
.addReg(SrcReg)
.addReg(ParityRegister);
if (Opc == AMDGPU::S_XOR_B32) {
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), DstReg)
.addReg(SrcReg)
.addReg(ParityRegister);
} else {
Register DestSub0 =
MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
Register DestSub1 =
MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);

const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
const TargetRegisterClass *SrcSubRC =
TRI->getSubRegisterClass(SrcRC, AMDGPU::sub0);

MachineOperand Op1L = TII->buildExtractSubRegOrImm(
MI, MRI, MI.getOperand(1), SrcRC, AMDGPU::sub0, SrcSubRC);
MachineOperand Op1H = TII->buildExtractSubRegOrImm(
MI, MRI, MI.getOperand(1), SrcRC, AMDGPU::sub1, SrcSubRC);

BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), DestSub0)
.add(Op1L)
.addReg(ParityRegister);

BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), DestSub1)
.add(Op1H)
.addReg(ParityRegister);

BuildMI(BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), DstReg)
.addReg(DestSub0)
.addImm(AMDGPU::sub0)
.addReg(DestSub1)
.addImm(AMDGPU::sub1);
}
break;
}
case AMDGPU::S_SUB_I32: {
Expand Down Expand Up @@ -5643,6 +5681,15 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
.addReg(LaneValueHiReg)
.addImm(AMDGPU::sub1);
switch (Opc) {
case AMDGPU::S_OR_B64:
case AMDGPU::S_AND_B64:
case AMDGPU::S_XOR_B64: {
NewAccumulator = BuildMI(*ComputeLoop, I, DL, TII->get(Opc), DstReg)
.addReg(Accumulator->getOperand(0).getReg())
.addReg(LaneValue->getOperand(0).getReg())
.setOperandDead(3); // Dead scc
break;
}
case AMDGPU::V_CMP_GT_I64_e64:
case AMDGPU::V_CMP_GT_U64_e64:
case AMDGPU::V_CMP_LT_I64_e64:
Expand Down Expand Up @@ -5751,10 +5798,16 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_SUB_U64_PSEUDO);
case AMDGPU::WAVE_REDUCE_AND_PSEUDO_B32:
return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_AND_B32);
case AMDGPU::WAVE_REDUCE_AND_PSEUDO_B64:
return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_AND_B64);
case AMDGPU::WAVE_REDUCE_OR_PSEUDO_B32:
return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_OR_B32);
case AMDGPU::WAVE_REDUCE_OR_PSEUDO_B64:
return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_OR_B64);
case AMDGPU::WAVE_REDUCE_XOR_PSEUDO_B32:
return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_XOR_B32);
case AMDGPU::WAVE_REDUCE_XOR_PSEUDO_B64:
return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_XOR_B64);
case AMDGPU::S_UADDO_PSEUDO:
case AMDGPU::S_USUBO_PSEUDO: {
const DebugLoc &DL = MI.getDebugLoc();
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/AMDGPU/SIInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -369,6 +369,9 @@ defvar Operations = [
WaveReduceOp<"max", "I64", i64, SGPR_64, VSrc_b64>,
WaveReduceOp<"add", "U64", i64, SGPR_64, VSrc_b64>,
WaveReduceOp<"sub", "U64", i64, SGPR_64, VSrc_b64>,
WaveReduceOp<"and", "B64", i64, SGPR_64, VSrc_b64>,
WaveReduceOp<"or", "B64", i64, SGPR_64, VSrc_b64>,
WaveReduceOp<"xor", "B64", i64, SGPR_64, VSrc_b64>,
];

foreach Op = Operations in {
Expand Down
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