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[AMDGPU][True16][GlobalISel] Fix v2*16 build_vector patterns #151496

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Merged
mbrkusanin merged 4 commits into from
Aug 4, 2025
Merged

[AMDGPU][True16][GlobalISel] Fix v2*16 build_vector patterns #151496

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e0ac143
[AMDGPU][True16][GlobalISel] Fix v2*16 build_vector patterns
mbrkusanin Jul 31, 2025
d09d9c0
use VGPR_16 for True16 pattern
mbrkusanin Jul 31, 2025
aed62ff
move pattern
mbrkusanin Jul 31, 2025
345937e
Fix FileCheck prefix names
mbrkusanin Aug 1, 2025
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17 changes: 14 additions & 3 deletions llvm/lib/Target/AMDGPU/SIInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -3543,14 +3543,21 @@ def : GCNPat <
(vecTy (UniformBinFrag<build_vector> (Ty undef), (Ty SReg_32:$src1))),
(S_LSHL_B32 SReg_32:$src1, (i32 16))
>;
}

def : GCNPat <
(vecTy (DivergentBinFrag<build_vector> (Ty undef), (Ty VGPR_32:$src1))),
(vecTy (V_LSHLREV_B32_e64 (i32 16), VGPR_32:$src1))
>;
} // End True16Predicate = ...
} // End foreach Ty = ...
}
} // End AddedComplexity = 1

let True16Predicate = UseRealTrue16Insts in
def : GCNPat <
(v2i16 (DivergentBinFrag<build_vector> (i16 undef), (i16 (trunc i32:$src1)))),
(REG_SEQUENCE VGPR_32, (i16 (IMPLICIT_DEF)), lo16,
(i16 (EXTRACT_SUBREG VGPR_32:$src1, lo16)), hi16)
>;

let SubtargetPredicate = HasVOP3PInsts in {
foreach p = [NotHasTrue16BitInsts, UseFakeTrue16Insts] in
Expand Down Expand Up @@ -3599,7 +3606,11 @@ def : GCNPat <
>;
def : GCNPat <
(vecTy (DivergentBinFrag<build_vector> (Ty VGPR_16:$src0), (Ty undef))),
(REG_SEQUENCE VGPR_32, $src0, lo16, (IMPLICIT_DEF), hi16)
(REG_SEQUENCE VGPR_32, $src0, lo16, (Ty (IMPLICIT_DEF)), hi16)
>;
def : GCNPat <
(vecTy (DivergentBinFrag<build_vector> (Ty undef), (Ty VGPR_16:$src1))),
(REG_SEQUENCE VGPR_32, (Ty (IMPLICIT_DEF)), lo16, (Ty VGPR_16:$src1), hi16)
>;
}

Expand Down
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