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[RISC-V]Implement -m{,no}fence-tso #151638

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[RISC-V]Implement -m{,no}fence-tso #151638

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1714ccb
[RISC-V]Implement -m{,no}fence-tso
ChunyuLiao Aug 1, 2025
3544707
making the default case command line shorter, not add -no-fence-tso
ChunyuLiao Aug 1, 2025
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7 changes: 7 additions & 0 deletions clang/include/clang/Driver/Options.td
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Original file line number Diff line number Diff line change
Expand Up @@ -5120,6 +5120,13 @@ def msave_restore : Flag<["-"], "msave-restore">, Group<m_riscv_Features_Group>,
HelpText<"Enable using library calls for save and restore">;
def mno_save_restore : Flag<["-"], "mno-save-restore">, Group<m_riscv_Features_Group>,
HelpText<"Disable using library calls for save and restore">;
def mfence_tso : Flag<["-"], "mfence-tso">,
Group<m_Group>,
HelpText<"Enable using fence-tso">;
def mno_fence_tso : Flag<["-"], "mno-fence-tso">,
Group<m_Group>,
HelpText<"Disable using fence-tso">;

} // let Flags = [TargetSpecific]
let Flags = [TargetSpecific] in {
def menable_experimental_extensions : Flag<["-"], "menable-experimental-extensions">, Group<m_Group>,
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4 changes: 4 additions & 0 deletions clang/lib/Driver/ToolChains/Arch/RISCV.cpp
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Expand Up @@ -142,6 +142,10 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
Features.push_back("-relax");
}

// -mfence-tso is default, unless -mno-fence-tso is specified.
if (Args.hasFlag(options::OPT_mno_fence_tso, options::OPT_mfence_tso, false))
Features.push_back("+no-fence-tso");

// If -mstrict-align, -mno-strict-align, -mscalar-strict-align, or
// -mno-scalar-strict-align is passed, use it. Otherwise, the
// unaligned-scalar-mem is enabled if the CPU supports it or the target is
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8 changes: 8 additions & 0 deletions clang/test/Driver/riscv-features.c
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Expand Up @@ -29,6 +29,14 @@
// DEFAULT-NOT: "-target-feature" "-save-restore"
// DEFAULT-NOT: "-target-feature" "+save-restore"

// RUN: %clang --target=riscv32-unknown-elf -### %s -mfence-tso 2>&1 | FileCheck %s -check-prefix=FENCE-TSO
// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-fence-tso 2>&1 | FileCheck %s -check-prefix=NO-FENCE-TSO

// FENCE-TSO-NOT: "-target-feature" "-no-fence-tso"
// NO-FENCE-TSO: "-target-feature" "+no-fence-tso"
// DEFAULT-NOT: "-target-feature" "-no-fence-tso"
// DEFAULT-NOT: "-target-feature" "+no-fence-tso"

// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-strict-align 2>&1 | FileCheck %s -check-prefixes=FAST-SCALAR-UNALIGNED-ACCESS,FAST-VECTOR-UNALIGNED-ACCESS
// RUN: %clang --target=riscv32-unknown-elf -### %s -mstrict-align 2>&1 | FileCheck %s -check-prefixes=NO-FAST-SCALAR-UNALIGNED-ACCESS,NO-FAST-VECTOR-UNALIGNED-ACCESS
// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-scalar-strict-align 2>&1 | FileCheck %s -check-prefix=FAST-SCALAR-UNALIGNED-ACCESS
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3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -1678,6 +1678,9 @@ foreach i = {1-31} in
def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
"true", "Enable save/restore.">;

def FeatureNoFenceTso : SubtargetFeature<"no-fence-tso", "EnableFenceTso",
"false", "Don't use fence.tso.">;

def FeatureNoTrailingSeqCstFence : SubtargetFeature<"no-trailing-seq-cst-fence",
"EnableTrailingSeqCstFence",
"false",
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10 changes: 10 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Expand Up @@ -6688,6 +6688,16 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
// MEMBARRIER is a compiler barrier; it codegens to a no-op.
return DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));

if (!Subtarget.enableFenceTso() &&
FenceOrdering == AtomicOrdering::AcquireRelease) {
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
SDValue Op1 =
DAG.getTargetConstant((unsigned)AtomicOrdering::SequentiallyConsistent,
dl, TLI.getFenceOperandTy(DAG.getDataLayout()));
return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Op.getOperand(0), Op1,
Op.getOperand(2));
}

return Op;
}

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20 changes: 20 additions & 0 deletions llvm/test/CodeGen/RISCV/atomic-fence.ll
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Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck --check-prefixes=CHECK,WMO %s
; RUN: llc -mtriple=riscv32 -mattr=+no-fence-tso -verify-machineinstrs < %s \
; RUN: | FileCheck --check-prefixes=CHECK,NTSO %s
; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck --check-prefixes=CHECK,WMO %s
; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso -verify-machineinstrs < %s \
Expand All @@ -11,13 +13,21 @@
; RUN: | FileCheck --check-prefixes=CHECK,WMO %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso -verify-machineinstrs < %s \
; RUN: | FileCheck --check-prefixes=CHECK,TSO %s
; RUN: llc -mtriple=riscv64 -mattr=+no-fence-tso -verify-machineinstrs < %s \
; RUN: | FileCheck --check-prefixes=CHECK,NTSO %s


define void @fence_acquire() nounwind {
; WMO-LABEL: fence_acquire:
; WMO: # %bb.0:
; WMO-NEXT: fence r, rw
; WMO-NEXT: ret
;
; NTSO-LABEL: fence_acquire:
; NTSO: # %bb.0:
; NTSO-NEXT: fence r, rw
; NTSO-NEXT: ret
;
; TSO-LABEL: fence_acquire:
; TSO: # %bb.0:
; TSO-NEXT: #MEMBARRIER
Expand All @@ -32,6 +42,11 @@ define void @fence_release() nounwind {
; WMO-NEXT: fence rw, w
; WMO-NEXT: ret
;
; NTSO-LABEL: fence_release:
; NTSO: # %bb.0:
; NTSO-NEXT: fence rw, w
; NTSO-NEXT: ret
;
; TSO-LABEL: fence_release:
; TSO: # %bb.0:
; TSO-NEXT: #MEMBARRIER
Expand All @@ -46,6 +61,11 @@ define void @fence_acq_rel() nounwind {
; WMO-NEXT: fence.tso
; WMO-NEXT: ret
;
; NTSO-LABEL: fence_acq_rel:
; NTSO: # %bb.0:
; NTSO-NEXT: fence rw, rw
; NTSO-NEXT: ret
;
; TSO-LABEL: fence_acq_rel:
; TSO: # %bb.0:
; TSO-NEXT: #MEMBARRIER
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/RISCV/features-info.ll
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Expand Up @@ -61,6 +61,7 @@
; CHECK-NEXT: m - 'M' (Integer Multiplication and Division).
; CHECK-NEXT: mips-p8700 - MIPS p8700 processor.
; CHECK-NEXT: no-default-unroll - Disable default unroll preference..
; CHECK-NEXT: no-fence-tso - Don't use fence.tso..
; CHECK-NEXT: no-sink-splat-operands - Disable sink splat operands to enable .vx, .vf,.wx, and .wf instructions.
; CHECK-NEXT: no-trailing-seq-cst-fence - Disable trailing fence for seq-cst store..
; CHECK-NEXT: optimized-nf2-segment-load-store - vlseg2eN.v and vsseg2eN.v are implemented as a wide memory op and shuffle.
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