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[AArch64] Drop poison flags when lowering absolute difference patterns. #152130

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Merged
rj-jesus merged 2 commits into from
Aug 6, 2025
Merged

[AArch64] Drop poison flags when lowering absolute difference patterns. #152130

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cb2cc62
[AArch64] Drop poison flags when lowering absolute difference patterns.
rj-jesus Aug 4, 2025
08ec67a
Drop flags first.
rj-jesus Aug 5, 2025
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11 changes: 8 additions & 3 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -11398,13 +11398,18 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(
// select_cc lhs, rhs, sub(rhs, lhs), sub(lhs, rhs), cc ->
// select_cc lhs, rhs, neg(sub(lhs, rhs)), sub(lhs, rhs), cc
// The second forms can be matched into subs+cneg.
// NOTE: Drop poison generating flags from the negated operand to avoid
// inadvertently propagating poison after the canonicalisation.
if (TVal.getOpcode() == ISD::SUB && FVal.getOpcode() == ISD::SUB) {
if (TVal.getOperand(0) == LHS && TVal.getOperand(1) == RHS &&
FVal.getOperand(0) == RHS && FVal.getOperand(1) == LHS)
FVal.getOperand(0) == RHS && FVal.getOperand(1) == LHS) {
TVal->dropFlags(SDNodeFlags::PoisonGeneratingFlags);
FVal = DAG.getNegative(TVal, DL, TVal.getValueType());
else if (TVal.getOperand(0) == RHS && TVal.getOperand(1) == LHS &&
FVal.getOperand(0) == LHS && FVal.getOperand(1) == RHS)
} else if (TVal.getOperand(0) == RHS && TVal.getOperand(1) == LHS &&
FVal.getOperand(0) == LHS && FVal.getOperand(1) == RHS) {
FVal->dropFlags(SDNodeFlags::PoisonGeneratingFlags);
TVal = DAG.getNegative(FVal, DL, FVal.getValueType());
}
}

unsigned Opcode = AArch64ISD::CSEL;
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