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[AMDGPU] Enable CodeGen for v_pk_fma_bf16 #152578

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Merged
merged 2 commits into from
Aug 7, 2025
Merged

[AMDGPU] Enable CodeGen for v_pk_fma_bf16 #152578

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f44daa1
[AMDGPU] bf16 clamp folding
rampitec Aug 7, 2025
6a9971d
[AMDGPU] Enable CodeGen for v_pk_fma_bf16
rampitec Aug 7, 2025
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10 changes: 7 additions & 3 deletions llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2081,7 +2081,9 @@ SIFoldOperandsImpl::isClamp(const MachineInstr &MI) const {
case AMDGPU::V_MAX_F16_fake16_e64:
case AMDGPU::V_MAX_F64_e64:
case AMDGPU::V_MAX_NUM_F64_e64:
case AMDGPU::V_PK_MAX_F16: {
case AMDGPU::V_PK_MAX_F16:
case AMDGPU::V_MAX_BF16_PSEUDO_e64:
case AMDGPU::V_PK_MAX_NUM_BF16: {
if (MI.mayRaiseFPException())
return nullptr;

Expand All @@ -2108,8 +2110,10 @@ SIFoldOperandsImpl::isClamp(const MachineInstr &MI) const {

// Having a 0 op_sel_hi would require swizzling the output in the source
// instruction, which we can't do.
unsigned UnsetMods = (Op == AMDGPU::V_PK_MAX_F16) ? SISrcMods::OP_SEL_1
: 0u;
unsigned UnsetMods =
(Op == AMDGPU::V_PK_MAX_F16 || Op == AMDGPU::V_PK_MAX_NUM_BF16)
? SISrcMods::OP_SEL_1
: 0u;
if (Src0Mods != UnsetMods && Src1Mods != UnsetMods)
return nullptr;
return Src0;
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6106,6 +6106,7 @@ bool SITargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
case MVT::f64:
return true;
case MVT::f16:
case MVT::bf16:
return Subtarget->has16BitInsts() && !denormalModeIsFlushAllF64F16(MF);
default:
break;
Expand Down
52 changes: 31 additions & 21 deletions llvm/test/CodeGen/AMDGPU/bf16-math.ll
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Expand Up @@ -368,11 +368,11 @@ define amdgpu_ps float @test_clamp_v2bf16_s(<2 x bfloat> inreg %src) {
define amdgpu_ps bfloat @test_clamp_bf16_folding(bfloat %src) {
; GCN-LABEL: test_clamp_bf16_folding:
; GCN: ; %bb.0:
; GCN-NEXT: v_exp_bf16_e32 v0, v0
; GCN-NEXT: v_nop
; GCN-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GCN-NEXT: v_pk_max_num_bf16 v0, v0, v0 clamp
; GCN-NEXT: v_exp_bf16_e64 v0, v0 clamp
; GCN-NEXT: ; return to shader part epilog



%exp = call bfloat @llvm.exp2.bf16(bfloat %src)
%max = call bfloat @llvm.maxnum.bf16(bfloat %exp, bfloat 0.0)
%clamp = call bfloat @llvm.minnum.bf16(bfloat %max, bfloat 1.0)
Expand All @@ -382,10 +382,11 @@ define amdgpu_ps bfloat @test_clamp_bf16_folding(bfloat %src) {
define amdgpu_ps float @test_clamp_v2bf16_folding(<2 x bfloat> %src0, <2 x bfloat> %src1) {
; GCN-LABEL: test_clamp_v2bf16_folding:
; GCN: ; %bb.0:
; GCN-NEXT: v_pk_mul_bf16 v0, v0, v1
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_pk_max_num_bf16 v0, v0, v0 clamp
; GCN-NEXT: v_pk_mul_bf16 v0, v0, v1 clamp
; GCN-NEXT: ; return to shader part epilog



%mul = fmul <2 x bfloat> %src0, %src1
%max = call <2 x bfloat> @llvm.maxnum.v2bf16(<2 x bfloat> %mul, <2 x bfloat> <bfloat 0.0, bfloat 0.0>)
%clamp = call <2 x bfloat> @llvm.minnum.v2bf16(<2 x bfloat> %max, <2 x bfloat> <bfloat 1.0, bfloat 1.0>)
Expand All @@ -396,11 +397,12 @@ define amdgpu_ps float @test_clamp_v2bf16_folding(<2 x bfloat> %src0, <2 x bfloa
define amdgpu_ps void @v_test_mul_add_v2bf16_vvv(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) {
; GCN-LABEL: v_test_mul_add_v2bf16_vvv:
; GCN: ; %bb.0:
; GCN-NEXT: v_pk_mul_bf16 v2, v2, v3
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_pk_add_bf16 v2, v2, v4
; GCN-NEXT: v_pk_fma_bf16 v2, v2, v3, v4
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm



%mul = fmul contract <2 x bfloat> %a, %b
%add = fadd contract <2 x bfloat> %mul, %c
store <2 x bfloat> %add, ptr addrspace(1) %out
Expand All @@ -410,11 +412,12 @@ define amdgpu_ps void @v_test_mul_add_v2bf16_vvv(ptr addrspace(1) %out, <2 x bfl
define amdgpu_ps void @v_test_mul_add_v2bf16_vss(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> inreg %b, <2 x bfloat> inreg %c) {
; GCN-LABEL: v_test_mul_add_v2bf16_vss:
; GCN: ; %bb.0:
; GCN-NEXT: v_pk_mul_bf16 v2, v2, s0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_pk_add_bf16 v2, v2, s1
; GCN-NEXT: v_pk_fma_bf16 v2, v2, s0, s1
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm

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what happens to these gaps?

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Somebody was removing outdated checks. I can regenerate all of that after it lands cleanly. Update script will remove it.



%mul = fmul contract <2 x bfloat> %a, %b
%add = fadd contract <2 x bfloat> %mul, %c
store <2 x bfloat> %add, ptr addrspace(1) %out
Expand All @@ -424,11 +427,14 @@ define amdgpu_ps void @v_test_mul_add_v2bf16_vss(ptr addrspace(1) %out, <2 x bfl
define amdgpu_ps void @v_test_mul_add_v2bf16_sss(ptr addrspace(1) %out, <2 x bfloat> inreg %a, <2 x bfloat> inreg %b, <2 x bfloat> inreg %c) {
; GCN-LABEL: v_test_mul_add_v2bf16_sss:
; GCN: ; %bb.0:
; GCN-NEXT: v_pk_mul_bf16 v2, s0, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_pk_add_bf16 v2, v2, s2
; GCN-NEXT: v_pk_fma_bf16 v2, s0, s1, v2
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm



%mul = fmul contract <2 x bfloat> %a, %b
%add = fadd contract <2 x bfloat> %mul, %c
store <2 x bfloat> %add, ptr addrspace(1) %out
Expand All @@ -438,11 +444,12 @@ define amdgpu_ps void @v_test_mul_add_v2bf16_sss(ptr addrspace(1) %out, <2 x bfl
define amdgpu_ps void @v_test_mul_add_v2bf16_vsc(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> inreg %b) {
; GCN-LABEL: v_test_mul_add_v2bf16_vsc:
; GCN: ; %bb.0:
; GCN-NEXT: v_pk_mul_bf16 v2, v2, s0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_pk_add_bf16 v2, v2, 0.5 op_sel_hi:[1,0]
; GCN-NEXT: v_pk_fma_bf16 v2, v2, s0, 0.5 op_sel_hi:[1,1,0]
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm



%mul = fmul contract <2 x bfloat> %a, %b
%add = fadd contract <2 x bfloat> %mul, <bfloat 0.5, bfloat 0.5>
store <2 x bfloat> %add, ptr addrspace(1) %out
Expand All @@ -452,11 +459,14 @@ define amdgpu_ps void @v_test_mul_add_v2bf16_vsc(ptr addrspace(1) %out, <2 x bfl
define amdgpu_ps void @v_test_mul_add_v2bf16_vll(ptr addrspace(1) %out, <2 x bfloat> %a) {
; GCN-LABEL: v_test_mul_add_v2bf16_vll:
; GCN: ; %bb.0:
; GCN-NEXT: v_pk_mul_bf16 v2, 0x42c83f80, v2
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_pk_add_bf16 v2, 0x43484000, v2
; GCN-NEXT: s_mov_b32 s0, 0x43484000
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GCN-NEXT: v_pk_fma_bf16 v2, 0x42c83f80, v2, s0
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm



%mul = fmul contract <2 x bfloat> %a, <bfloat 1.0, bfloat 100.0>
%add = fadd contract <2 x bfloat> %mul, <bfloat 2.0, bfloat 200.0>
store <2 x bfloat> %add, ptr addrspace(1) %out
Expand Down
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