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Merged
dpaoliello merged 3 commits into from
Aug 12, 2025
Merged

[Arm64EC] Add support for half #152843

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97b7f11
[Arm64EC] Add support for `half`
tgross35 Aug 9, 2025
66839d2
Change mangling, get rid of EC label with regex
tgross35 Aug 12, 2025
ae81cbd
Fix generic test regex
tgross35 Aug 12, 2025
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6 changes: 4 additions & 2 deletions llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -317,7 +317,8 @@ ThunkArgInfo AArch64Arm64ECCallLowering::canonicalizeThunkType(
};

if (T->isHalfTy()) {
Out << "h";
// Prefix with `llvm` since MSVC doesn't specify `_Float16`
Out << "__llvm_h__";
return direct(T);
}

Expand Down Expand Up @@ -350,7 +351,8 @@ ThunkArgInfo AArch64Arm64ECCallLowering::canonicalizeThunkType(
if (ElementTy->isHalfTy() || ElementTy->isFloatTy() ||
ElementTy->isDoubleTy()) {
if (ElementTy->isHalfTy())
Out << "H";
// Prefix with `llvm` since MSVC doesn't specify `_Float16`
Out << "__llvm_H__";
else if (ElementTy->isFloatTy())
Out << "F";
else if (ElementTy->isDoubleTy())
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -87,8 +87,8 @@ define i64 @simple_integers(i8, i16, i32, i64) nounwind {

; NOTE: Only half, float, and double are supported.
define double @simple_floats(half, float, double) nounwind {
; CHECK-LABEL: .def $ientry_thunk$cdecl$d$hfd;
; CHECK: .section .wowthk$aa,"xr",discard,$ientry_thunk$cdecl$d$hfd
; CHECK-LABEL: .def $ientry_thunk$cdecl$d$__llvm_h__fd;
; CHECK: .section .wowthk$aa,"xr",discard,$ientry_thunk$cdecl$d$__llvm_h__fd
; CHECK: // %bb.0:
; CHECK-NEXT: stp q6, q7, [sp, #-176]! // 32-byte Folded Spill
; CHECK-NEXT: .seh_save_any_reg_px q6, 176
Expand Down Expand Up @@ -600,7 +600,7 @@ start:
; CHECK-NEXT: .symidx $ientry_thunk$cdecl$i8$i8i8i8i8
; CHECK-NEXT: .word 1
; CHECK-NEXT: .symidx "#simple_floats"
; CHECK-NEXT: .symidx $ientry_thunk$cdecl$d$hfd
; CHECK-NEXT: .symidx $ientry_thunk$cdecl$d$__llvm_h__fd
; CHECK-NEXT: .word 1
; CHECK-NEXT: .symidx "#has_varargs"
; CHECK-NEXT: .symidx $ientry_thunk$cdecl$v$varargs
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
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Expand Up @@ -95,8 +95,8 @@ declare i64 @simple_integers(i8, i16, i32, i64) nounwind;

; NOTE: Only half, float, and double are supported.
declare double @simple_floats(half, float, double) nounwind;
; CHECK-LABEL: .def $iexit_thunk$cdecl$d$hfd;
; CHECK: .section .wowthk$aa,"xr",discard,$iexit_thunk$cdecl$d$hfd
; CHECK-LABEL: .def $iexit_thunk$cdecl$d$__llvm_h__fd;
; CHECK: .section .wowthk$aa,"xr",discard,$iexit_thunk$cdecl$d$__llvm_h__fd
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: .seh_stackalloc 48
Expand Down Expand Up @@ -129,8 +129,8 @@ declare double @simple_floats(half, float, double) nounwind;
; CHECK-NEXT: adrp x11, simple_floats
; CHECK-NEXT: add x11, x11, :lo12:simple_floats
; CHECK-NEXT: ldr x8, [x8, :lo12:__os_arm64x_check_icall]
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$d$hfd
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$d$hfd
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$d$__llvm_h__fd
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$d$__llvm_h__fd
; CHECK-NEXT: blr x8
; CHECK-NEXT: .seh_startepilogue
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
Expand Down Expand Up @@ -283,8 +283,8 @@ declare void @has_aligned_sret(ptr align 32 sret(%TSRet)) nounwind;
; CHECK: .seh_endproc

declare [2 x i8] @small_array([2 x i8], [2 x half], [2 x float]) nounwind;
; CHECK-LABEL: .def $iexit_thunk$cdecl$m2$m2H4F8;
; CHECK: .section .wowthk$aa,"xr",discard,$iexit_thunk$cdecl$m2$m2H4F8
; CHECK-LABEL: .def $iexit_thunk$cdecl$m2$m2__llvm_H__4F8;
; CHECK: .section .wowthk$aa,"xr",discard,$iexit_thunk$cdecl$m2$m2__llvm_H__4F8
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #80
; CHECK-NEXT: .seh_stackalloc 80
Expand Down Expand Up @@ -328,8 +328,8 @@ declare [2 x i8] @small_array([2 x i8], [2 x half], [2 x float]) nounwind;
; CHECK-NEXT: adrp x11, small_array
; CHECK-NEXT: add x11, x11, :lo12:small_array
; CHECK-NEXT: ldr x8, [x8, :lo12:__os_arm64x_check_icall]
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$m2$m2H4F8
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$m2$m2H4F8
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$m2$m2__llvm_H__4F8
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$m2$m2__llvm_H__4F8
; CHECK-NEXT: blr x8
; CHECK-NEXT: .seh_startepilogue
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
Expand Down Expand Up @@ -580,7 +580,7 @@ declare <8 x i16> @large_vector(<8 x i16> %0) nounwind;
; CHECK-NEXT: .symidx simple_integers
; CHECK-NEXT: .word 0
; CHECK-NEXT: .symidx simple_floats
; CHECK-NEXT: .symidx $iexit_thunk$cdecl$d$hfd
; CHECK-NEXT: .symidx $iexit_thunk$cdecl$d$__llvm_h__fd
; CHECK-NEXT: .word 4
; CHECK-NEXT: .symidx "#simple_floats$exit_thunk"
; CHECK-NEXT: .symidx simple_floats
Expand All @@ -604,7 +604,7 @@ declare <8 x i16> @large_vector(<8 x i16> %0) nounwind;
; CHECK-NEXT: .symidx has_aligned_sret
; CHECK-NEXT: .word 0
; CHECK-NEXT: .symidx small_array
; CHECK-NEXT: .symidx $iexit_thunk$cdecl$m2$m2H4F8
; CHECK-NEXT: .symidx $iexit_thunk$cdecl$m2$m2__llvm_H__4F8
; CHECK-NEXT: .word 4
; CHECK-NEXT: .symidx "#small_array$exit_thunk"
; CHECK-NEXT: .symidx small_array
Expand Down
14 changes: 5 additions & 9 deletions llvm/test/CodeGen/Generic/half.ll
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Expand Up @@ -7,7 +7,7 @@
; RUN: %if aarch64-registered-target %{ llc %s -o - -mtriple=aarch64-apple-darwin | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if aarch64-registered-target %{ llc %s -o - -mtriple=aarch64-pc-windows-msvc | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if aarch64-registered-target %{ llc %s -o - -mtriple=aarch64-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if aarch64-registered-target %{ llc %s -o - -mtriple=arm64ec-pc-windows-msvc | FileCheck %s --check-prefixes=EC,CHECK %}
; RUN: %if aarch64-registered-target %{ llc %s -o - -mtriple=arm64ec-pc-windows-msvc | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if amdgpu-registered-target %{ llc %s -o - -mtriple=amdgcn-amd-amdhsa | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if arc-registered-target %{ llc %s -o - -mtriple=arc-elf | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if arm-registered-target %{ llc %s -o - -mtriple=arm-unknown-linux-gnueabi | FileCheck %s --check-prefixes=ALL,CHECK %}
Expand Down Expand Up @@ -46,8 +46,7 @@
; RUN: %if xcore-registered-target %{ llc %s -o - -mtriple=xcore-unknown-unknown | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if xtensa-registered-target %{ llc %s -o - -mtriple=xtensa-none-elf | FileCheck %s --check-prefixes=ALL,CHECK %}

; Note that arm64ec labels don't have a `:` so use `EC`, other tests do need the
; `:` so directives with the function names don't get treated as labels.
; Note that arm64ec labels are quoted, hence the `{{"?}}:`.

; Codegen tests don't work the same for graphics targets. Add a dummy directive
; for filecheck, just make sure we don't crash.
Expand All @@ -60,8 +59,7 @@
; Regression test for https://github.com/llvm/llvm-project/issues/97981.

define half @from_bits(i16 %bits) nounwind {
; ALL-LABEL: from_bits:
; EC-LABEL: from_bits
; ALL-LABEL: from_bits{{"?}}:
; CHECK-NOT: __extend
; CHECK-NOT: __trunc
; CHECK-NOT: __gnu
Expand All @@ -71,8 +69,7 @@ define half @from_bits(i16 %bits) nounwind {
}

define i16 @to_bits(half %f) nounwind {
; ALL-LABEL: to_bits:
; EC-LABEL: to_bits
; ALL-LABEL: to_bits{{"}}:
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@dpaoliello dpaoliello Aug 12, 2025

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Suggested change
; ALL-LABEL: to_bits{{"}}:
; ALL-LABEL: to_bits{{"?}}:

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@tgross35 tgross35 Aug 12, 2025

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...totally forgot to retest this file, thanks. Updated (passes locally)

; CHECK-NOT: __extend
; CHECK-NOT: __trunc
; CHECK-NOT: __gnu
Expand All @@ -85,8 +82,7 @@ define i16 @to_bits(half %f) nounwind {
; https://github.com/llvm/llvm-project/issues/117337 and similar issues.

define half @check_freeze(half %f) nounwind {
; ALL-LABEL: check_freeze:
; EC-LABEL: check_freeze
; ALL-LABEL: check_freeze{{"}}:
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@dpaoliello dpaoliello Aug 12, 2025

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Suggested change
; ALL-LABEL: check_freeze{{"}}:
; ALL-LABEL: check_freeze{{"?}}:

%t0 = freeze half %f
ret half %t0
}
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