[AVR] Mulhi3/mulqi3 regression test

llvm/test/CodeGen/AVR/issue-151080-mod.ll

@@ -0,0 +1,58 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -O=3 -mtriple=avr-none -mcpu=attiny85 -verify-machineinstrs | FileCheck %s
+
+@c = dso_local local_unnamed_addr global i8 0, align 1
+define dso_local void @mod(i16 noundef %0) local_unnamed_addr addrspace(1) {
+; CHECK-LABEL: mod:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    push r14
+; CHECK-NEXT:    push r16
+; CHECK-NEXT:    push r17
+; CHECK-NEXT:    cpi r24, 10
+; CHECK-NEXT:    cpc r25, r1
+; CHECK-NEXT:    brlo .LBB0_2
+; CHECK-NEXT:  ; %bb.1:
+; CHECK-NEXT:    ldi r18, 205
+; CHECK-NEXT:    ldi r19, 204
+; CHECK-NEXT:    ldi r20, 0
+; CHECK-NEXT:    ldi r21, 0
+; CHECK-NEXT:    movw r22, r24
+; CHECK-NEXT:    mov r14, r24
+; CHECK-NEXT:    movw r24, r20
+; CHECK-NEXT:    rcall __mulsi3
+; CHECK-NEXT:    movw r16, r24
+; CHECK-NEXT:    lsr r17
+; CHECK-NEXT:    ror r16
+; CHECK-NEXT:    lsr r17
+; CHECK-NEXT:    ror r16
+; CHECK-NEXT:    lsr r17
+; CHECK-NEXT:    ror r16
+; CHECK-NEXT:    movw r24, r16
+; CHECK-NEXT:    rcall mod
+; CHECK-NEXT:    mov r24, r16
+; CHECK-NEXT:    ldi r22, -10
+; CHECK-NEXT:    rcall __mulqi3
+; CHECK-NEXT:    add r24, r14
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    ori r24, 48
+; CHECK-NEXT:    sts c, r24
+; CHECK-NEXT:    pop r17
+; CHECK-NEXT:    pop r16
+; CHECK-NEXT:    pop r14
+; CHECK-NEXT:    ret
+  %2 = icmp ugt i16 %0, 9
+  %3 = trunc i16 %0 to i8
+  br i1 %2, label %4, label %9
+4:                                                ; preds = %1
+  %5 = udiv i16 %0, 10
+  %6 = trunc i16 %5 to i8
+  %7 = mul i8 %6, -10
+  tail call addrspace(1) void @mod(i16 noundef %5)
+  %8 = add i8 %7, %3
+  br label %9
+9:                                                ; preds = %4, %1
+  %10 = phi i8 [ %3, %1 ], [ %8, %4 ]
+  %11 = or disjoint i8 %10, 48
+  store i8 %11, ptr @c, align 1
+  ret void
+}