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[Mips] Fixed libunwind::Registers_mips_o32::jumpto to allow for load delay #152942

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Merged
merged 4 commits into from
Sep 25, 2025
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Merged

[Mips] Fixed libunwind::Registers_mips_o32::jumpto to allow for load delay #152942

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0f46018
Update libunwind::Registers_mips_o32::jumpto to allow for load delay
Jade-Marker Aug 10, 2025
9c089f5
Update UnwindRegistersRestore.S
Jade-Marker Aug 10, 2025
8273a07
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Jade-Marker Sep 24, 2025
255e067
Merge branch 'main' into main
wzssyqa Sep 24, 2025
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9 changes: 6 additions & 3 deletions libunwind/src/UnwindRegistersRestore.S
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Original file line number Diff line number Diff line change
Expand Up @@ -1044,9 +1044,10 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv)
lw $27, (4 * 27)($4)
lw $28, (4 * 28)($4)
lw $29, (4 * 29)($4)
lw $30, (4 * 30)($4)
// load new pc into ra
lw $31, (4 * 32)($4)
//allow for load delay, so that ra address is new value when jumping
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Suggest:

// MIPS 1 has load delay slot. Ensure lw $31 and jr are separated by an instruction.

lw $30, (4 * 30)($4)
// jump to ra, load a0 in the delay slot
jr $31
lw $4, (4 * 4)($4)
Expand Down Expand Up @@ -1082,11 +1083,13 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind21Registers_mips_newabi6jumptoEv)
ld $2, (8 * 2)($4)
ld $3, (8 * 3)($4)
// skip a0 for now
.irp i,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
.irp i,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
ld $\i, (8 * \i)($4)
.endr
// load new pc into ra
ld $31, (8 * 32)($4)
ld $31, (4 * 32)($4)
//allow for load delay, so that ra address is new value when jumping
ld $30, (4 * 30)($4)
// jump to ra, load a0 in the delay slot
jr $31
ld $4, (8 * 4)($4)
Expand Down
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